39.5.3 Clocks

The SDADC bus clock (CLK_SDADC_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_SDADC_APB can be found in the Peripheral Clock Masking section.

A generic clock (GCLK_SDADC) is required to generate the CLK_SDADC for the SDADC analog module. This clock must be configured and enabled in the Generic Clock Controller (GCLK) before using the SDADC. The CLK_SDADC is the SDADC clock connected to the SDADC analog module and its range is between GCLK_SDADC/2, (if PRESCALER is 0) and GCLK_SDADC/512 (if PRESCALER is 255). Please refer to the CTRLB register for more details.

The SDADC data sampling clock CLK_SDADC_FS in the SDADC analog module is the CLK_SDADC/4.

This GCLK_SDADC is asynchronous to the bus clock (CLK_SDADC_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains.