28.4.2 Operation

The basic structure of the SERCOM serial engine is shown in Figure 28-2.

Registers with names in capital letters are synchronous to the system clock and accessible by the CPU, while those with names in lowercase letters can be configured to run on the GCLK_SERCOMx_CORE clock or an external clock.

The transmitter consists of a single write buffer and a shift register.

The receiver consists of a one-level (I²C), two-level (USART, SPI) receive buffer and a shift register.

The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external clock.

Address matching logic is incorporated to support both SPI and I²C operations.