17.5.5 Interrupts
The interrupt request line, also known as the interrupt vector, is connected to the interrupt controller. To use PAC interrupts, the interrupt controller must be configured in advance, including enabling the interrupt line globally. For further information, refer to the NVIC - Nested Vectored Interrupt Controller section.
Each interrupt source has an interrupt
flag which is in the Interrupt Flag Status and Clear registers listed below:
- AHB Client Bus Interrupt Flag Status and Clear (INTFLAGAHB) register
- Peripheral Interrupt Flag Status and Clear A (INTFLAGA) register
- Peripheral Interrupt Flag Status and Clear B(INTFLAGB) register
- Peripheral Interrupt Flag Status and Clear C(INTFLAGC) register
1’ to the corresponding bit in the
Interrupt Enable Set (INTENSET) register, and disabled by writing a ‘1’
to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register.An interrupt request is generated when the interrupt flag is set and the corresponding interrupt source is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the peripheral is reset. Refer to the INTFLAGAHB, INTFLAGA, INTFLAGB and INTFLAGC register description for details on how to clear interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate a single combined interrupt request to the NVIC. Therefore, the INTFLAG register must be read to determine what the interrupt condition is.
| Vector Name | Source Name | Condition | Dependency |
|---|---|---|---|
| PAC | FLASH | Access Error is detected by client Flash | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set |
| HSRAMCM0P | Access Error is detected by client SRAMCM0P | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| HSRAMDSU | Access Error is detected by client SRAMDSU | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| APBB | Access Error is detected by client APBB | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| APBA | Access Error is detected by client APBA | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| APBC | Access Error is detected by client APBC | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| SRAMDMAC | Access Error is detected by client SRAMDMAC | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| BROM | Access Error is detected by client BROM | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| PAC | Peripheral Access Error occurs while accessing PAC | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| PM | Peripheral Access Error occurs while accessing PM | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| MCLK | Peripheral Access Error occurs while accessing MCLK | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| RSTC | Peripheral Access Error occurs while accessing RSTC | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| OSCCTRL | Peripheral Access Error occurs while accessing OSCCTRL | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| SUPC | Peripheral Access Error occurs while accessing SUPC | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| GCLK | Peripheral Access Error occurs while accessing GCLK | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| WDT | Peripheral Access Error occurs while accessing WDT | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| RTC | Peripheral Access Error occurs while accessing RTC | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| EIC | Peripheral Access Error occurs while accessing EIC | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| PORT | Peripheral Access Error occurs while accessing PORT | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| DSU | Peripheral Access Error occurs while accessing DSU | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| NVMCTRL | Peripheral Access Error occurs while accessing NVMCTRL | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| DMAC | Peripheral Access Error occurs while accessing DMAC | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| MTB | Peripheral Access Error occurs while accessing MTB | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| HMATRIXHS | Peripheral Access Error occurs while accessing HMATRIXHS | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| EVSYS | Peripheral Access Error occurs while accessing EVSYS | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| SERCOMn | Peripheral Access Error occurs while accessing SERCOMn | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| TCn | Peripheral Access Error occurs while accessing TCn | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| TCCn | Peripheral Access Error occurs while accessing TCCn | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| ADC0 | Peripheral Access Error occurs while accessing ADC0 | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| AC | Peripheral Access Error occurs while accessing AC | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| CCL | Peripheral Access Error occurs while accessing CCL | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| PTC | Peripheral Access Error occurs while accessing PTC | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| SYSCTRL | Peripheral Access Error occurs while accessing SYSCTRL | The Peripheral Access Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set |