29.4.2.1.1 Synchronous Clock Operation

In Synchronous mode, the CTRLA.MODE bit field determines whether the transmission clock line (XCK) serves as an input or an output. The relationship between clock edges, data sampling, and data changes is the same for both internal and external clocks. Data input on the RxD pin is sampled on the opposite XCK clock edge from when data is driven on the TxD pin.

The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for RxD sampling, and which is used for TxD change:

When CTRLA.CPOL is ‘0’, the data will be changed on the rising edge of XCK, and sampled on the falling edge of XCK.

When CTRLA.CPOL is ‘1’, the data will be changed on the falling edge of XCK, and sampled on the rising edge of XCK.

When the clock is provided through XCK, the shift registers operate directly on the XCK clock. This means that XCK is not synchronized with the system clock and, therefore, can operate at frequencies up to the system frequency.