22.4.1 Initialization

The following registers are enable-protected, meaning that they can only be written when the TC is disabled (CTRLA.ENABLE =0):

  • Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits
  • Driver Control register (DRVCTRL)
  • Waveform Generation Control register (WAVE)
  • Event Control register (EVCTRL)

Writing to Enable-Protected bits and setting the CTRLA.ENABLE bit can be performed in a single 32-bit access of the CTRLA register. However, writing to Enable-Protected bits and clearing the CTRLA.ENABLE bit cannot be performed in a single 32-bit access.

Before enabling the TC, the peripheral must be configured by the following steps:
  1. Enable the TC bus clock (CLK_TCn_APB).
  2. Select 8-, 16- or 32-bit counter mode via the TC Mode bit field in the Control A register (CTRLA.MODE). The default mode is 16-bit.
  3. Select a waveform generation operation using the Waveform Generation Mode bit field in the Waveform Generation Control register (WAVE.WAVEGEN).
  4. If desired, the GCLK_TCn clock can be prescaled via the Prescaler bit field in the Control A register (CTRLA.PRESCALER).
    • If the prescaler is used, select a prescaler synchronization operation via the Prescaler and Counter Synchronization bit field in the Control A register (CTRLA.PRESYNC)
  5. If desired, enable one-shot operation by writing a ‘1’ to the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT).
  6. If desired, configure the counting direction to 'down' (starting from the TOP value) by writing a ‘1’ to the Counter Direction bit in the Control B register (CTRLBSET.DIR).
  7. If desired, for capture operation, enable the individual channels for capture by setting the Capture Channel n Enable bit field in the Control A register (CTRLA.CAPTEN).
  8. If desired, enable inversion of the waveform output or I/O pin input signal for individual channels by setting the Invert Enable bit field in the Driver Control register (DRVCTRL.INVEN).
Note: Two instances of the TC may share a peripheral clock channel. In this case, they cannot be configured to use different clock frequencies. Refer to the peripheral clock channel mapping of the Generic Clock Controller (GCLK) section and the Peripheral Channel Control (PCHCTRLm) register section to identify shared peripheral clocks.