22.4.2 Operation
The following definitions are used throughout the documentation:
| Name | Description |
|---|---|
| TOP | The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP value can be the same as Period (PER) or the Compare Channel 0 (CC0) register value depending on the Waveform Generator mode in the Waveform Output Operations section |
| ZERO | The counter is ZERO when it contains all zeroes |
| MAX | The counter reaches MAX when it contains all ones |
| UPDATE | The timer/counter signals an update when it reaches ZERO or TOP, depending on the direction settings |
| Timer | TC mode where increment/decrement/clear/reload operations are performed on every prescaled clock cycle |
| Counter | TC mode where increment/decrement/clear/reload operations are performed on each detected event |
| CC |
In compare operations, the CC registers are referred to as “compare channels.” In capture operations, the CC registers are referred to as “capture channels.” |
Each TC instance has 2 compare/capture channels (CC[n]).
The counter in the TC can either count events from the Event System, or clock ticks of the GCLK_TCn clock, which may be divided by the prescaler.
The counter value is passed to the CC[n] where it can be either compared to user-defined values or captured.
The CC[n] registers are using buffer registers (CCBUF[n]) for optimized timing. Each buffer register has a Buffer Valid (BUFV) flag, which signals when the buffer holds a new value.
The Counter register (COUNT) and the Compare and Capture registers, including buffers (CC[n] and CCBUF[n]) can be configured as 8-, 16- or 32-bit registers, each with a corresponding MAX values. The mode settings (CTRLA.MODE) determine the maximum range of the Counter register.
In 8-bit mode, a Period (PER) register and its Period Buffer (PERBUF) register are also available. The counter range and the operating frequency define the maximum time resolution achievable with the TC peripheral.
The TC can be set to count up or down. The counter value is continuously compared to the TOP or ZERO value to determine whether the counter has reached that value. On a comparison match, the TC can request DMA transactions, generate interrupts, or events for the Event System.
In a compare operation, the counter value is continuously compared to the values in the CC[n] registers. When a match occurs, the TC can request DMA transactions, generate interrupts, or events for the Event System. In Waveform Generator mode, these comparisons are used to set the waveform period or pulse width.
Capture operation can be enabled to perform input signal period and pulse width measurements, or to capture selectable edges from an I/O pin or internal event from Event System.