23.5.6 Events

The TCC can generate the following events:

Table 23-8. TCC Event Generators
Generator Name		Description	Event Type	Generating Clock Domain	Length of Event
Peripheral	Event	Description	Event Type	Generating Clock Domain	Length of Event
TCCn	OVF	Overflow/Underflow	Pulse	GCLK_TCCn	One GCLK_TCCn period
	TRG	Trigger	Pulse	GCLK_TCCn	One GCLK_TCCn period
	CNT	Counter	Pulse	GCLK_TCCn	One GCLK_TCCn period
	MC_n	Compare Match or Capture on compare/capture channel n	Pulse	GCLK_TCCn	One GCLK_TCCn period

Writing a ‘1’ to an Event Output Enable bit in the Event Control register (EVCTRL.xxEO) enables the corresponding output event. Writing a ‘0’ to this bit disables the corresponding output event.

The TCC can connect to the following events:

Table 23-9. Event Users
User Name		Description	Input Detection	Channel Path Type
Peripheral	Input	Description	Input Detection	Channel Path Type
TCCn	EV_n	Event Input n	Level/Edge	Asynchronous
TCCn	MC_n	Capture event n	Rising Edge	Asynchronous

Writing a ‘1’ to an Event Input Enable bit in the Event Control register (EVCTRL.xxEI) enables the corresponding action on an input event. Writing a ‘0’ to this bit disables the corresponding action on an input event.

Note: EVn input detection depends on the configuration of the Timer/Counter Event n Invert Enable bit in the Event Control register (EVCTRL.TCINVn) and the Timer/Counter Event Input n Action bit fields in the Event Control register (EVCTRL.EVACTn).

The event users can trigger the following actions:

Table 23-10. Event Actions
Event Input	Event Action	Description
EV_0	RETRIGGER	Counter retrigger
	COUNTEV	Count on event (increment or decrement, depending on counter direction)
	START	Counter start - Start counting on the event rising edge. Further events will not restart the counter; the counter will keep on counting using prescaled GCLK_TCCn, until it reaches TOP or ZERO, depending on the direction
	INC	Counter increment on event. This will increment the counter, irrespective of the counter direction
	COUNT_ASYNC	Count during active state of an asynchronous event (increment or decrement, depending on counter direction). In this case, the counter will be incremented or decremented on each cycle of the prescaled clock, as long as the event is active
	STAMP	Capture Time-stamp (overflow)
	FAULT_ASYNC	Non-recoverable fault
EV_1	RETRIGGER	Counter retrigger
	DIR_ASYNC	Counter direction control
	STOP	Stop the counter
	DEC	Decrement the counter on event
	PWP_ASYNC	Period and pulse width capture
	FAULT_ASYNC	Non-recoverable fault
MC_n	—	Capture event
MC_n	—	Generate a recoverable or non-recoverable fault

Refer to the EVSYS - Event System chapter for details on configuring the event system.

Note:

Counter retrigger is not supported if RAMP2 operation is used with a prescaler (CTRLA.PRESCALER != 0). RAMP2 operation can use the retrigger option only if the counter retrigger is synchronized with the next prescaler clock (CTRLA.PRESCYNC = PRESC).
If a retrigger event occurs exactly at the time a channel compare match occurs, the next waveform will be corrupted. To avoid this issue, use two channels to store two successive CC register values (n and n+1) and combine the related waveform outputs to provide signal redundancy.
See the Capture Operations and Recoverable Faults sections for more information on the Match or Capture input events (MCn).