22.5.5 Interrupts
The interrupt request line, also known as the interrupt vector, is connected to the interrupt controller. To use TC interrupts, the interrupt controller must be configured in advance, including enabling the interrupt line globally. For further information, refer to the NVIC - Nested Vectored Interrupt Controller section.
Each interrupt source has an interrupt flag
which is in the Interrupt Flag Status and Clear (INTFLAG) register. The flag is set when the
interrupt condition occurs. Each interrupt can be individually enabled by writing a
‘1’ to the corresponding bit in the Interrupt Enable Set (INTENSET)
register, and disabled by writing a ‘1’ to the corresponding bit in the
Interrupt Enable Clear (INTENCLR) register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt source is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the peripheral is reset. Refer to the INTFLAG register description for details on how to clear interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate a single combined interrupt request to the NVIC. Therefore, the INTFLAG register must be read to determine what the interrupt condition is.
| Vector Name | Source Name | Condition | Dependency |
|---|---|---|---|
| TCn | OVF | An overflow condition occurs | The Overflow Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.OVF) must be set |
| ERR | A new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt flag = ‘1’ | The Error Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.ERR) must be set | |
| MCn | A match with the compare condition or once CCn register contain a valid capture value | Match or Capture Channel n Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCn) must be set |