19.4.1 Initialization

The following DMAC registers and bits/bit fields are enable-protected, meaning they can only be written to when the DMAC is disabled (CTRL.DMAENABLE = 0):

• Descriptor Base Memory Address (BASEADDR) register
• Write-Back Memory Base Address (WRBADDR) register

The following DMAC bit is enable-protected, meaning it can only be written when both the DMAC and CRC are disabled (CTRL.DMAENABLE = 0 and CTRL.CRCENABLE = 0):

• Software Reset bit in the Control register (CTRL.SWRST)

The following DMA channel register and bit are enable-protected, meaning it can only be written to when the corresponding DMA channel is disabled (CHCTRLA.ENABLE = 0):

• Channel Control B (CHCTRLB) register, except for the Command (CHCTRLB.CMD) bit and the Channel Arbitration Level (CHCTRLB.LVL) bit
• Channel Software Reset bit in Channel Control A (CHCTRLA.SWRST) register

The following CRC registers are enable-protected, meaning they can only be written to when the CRC is disabled (CTRL.CRCENABLE = 0):

• CRC Control (CRCCTRL) register
• CRC Checksum (CRCCHKSUM) register

Enable-protection is indicated by the Enable-Protected property in the register description.

Before the DMA engine is enabled, it must be configured according to the following steps:

• The SRAM address of the descriptor memory section must be written to the Description Base Address (BASEADDR) register
• The SRAM address of the write-back memory section must be written to the Write-Back Memory Base Address (WRBADDR) register
• Priority level n of the arbiter must be enabled by writing a ‘1’ the Priority Level n Enable bit in the Control register (CTRL.LVLENn) for the arbiter to handle channels with priority level n
• Once the DMA engine is configured it can be enabled by setting the DMA Enable bit in the Control (CTRL.DMAENABLE) register

Before a DMA channel is enabled, both the channel itself and the corresponding first transfer descriptor must be configured according to the following steps:

• DMA channel configurations
  • The channel number of the DMA channel to be configured must be selected by writing to the Channel ID (CHID) register
  • Trigger action must be selected by writing to the Trigger Action bit field in the Channel Control B (CHCTRLB.TRIGACT) register
  • Trigger source must be selected by writing to the Trigger Source bit field in the Channel Control B (CHCTRLB.TRIGSRC) register
• Transfer Descriptor configurations
  • The size of each access on the data transfer bus must be selected by writing the Beat Size bit field in the Block Transfer Control (BTCTRL.BEATSIZE) register
  • The transfer descriptor must be made valid by writing a ‘1’ to the Valid bit in the Block Transfer Control (BTCTRL.VALID) register
  • The number of beats in the block transfer must be set by writing to the Block Transfer Count (BTCNT) register
  • The source address for the block transfer must be set by writing to the Block Transfer Source Address (SRCADDR) register
  • The destination address for the block transfer must be set by writing to the Block Transfer Destination Address (DSTADDR) register
• Once the selected DMA channel is configured it can be enabled by setting the Channel Enable bit in the Channel Control A register (CHCTRLA.ENABLE)

If CRC calculation is needed, the CRC engine must be configured before it is enabled, as outlined by the following steps:

• The CRC input source must selected by writing to the CRC Input Source bit field in the CRC Control (CRCCTRL.CRCSRC) register
• The type of CRC calculation must be selected by writing to the CRC Polynomial Type bit field in the CRC Control (CRCCTRL.CRCPOLY) register
• If I/O is selected as the input source, the beat size must be selected by writing to the CRC Beat Size bit field in the CRC Control (CRCCTRL.CRCBEATSIZE) register
• Once the CRC engine is configured it can be enabled by setting the CRC Enable bit in the Control (CTRL.CRCENABLE) register