29.5.4 DMA

The USART generates the following DMA requests:

• Receive Complete (RXC): The request is set when data is available in the receive buffer (RX DATA). The request is cleared when DATA is read.
• Data Register Empty (DRE): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when DATA is written.

The DMA request lines are connected to the DMA Controller (DMAC). The DMAC must be configured before using the USART’s DMA requests. Refer to the DMAC – Direct Memory Access Controller chapter for details.