8 TCD with XOSCHF and PLL

To use XOSCHF as clock source for the Phase-Lock Loop (PLL), first enable the XOSCHF similarly to first two use cases. The crystal or input clock frequency must be at least 16 MHz and can be multiplied two or three times, giving an output frequency up to 48 MHz.

	/* Enable crystal oscillator with frequency range 16 MHz and 4K cycles start-up time */
	ccp_write_io((uint8_t *) &CLKCTRL.XOSCHFCTRLA, CLKCTRL_RUNSTDBY_bm
	             | CLKCTRL_CSUTHF_4K_gc
	             | CLKCTRL_FRQRANGE_16M_gc
	             | CLKCTRL_SELHF_CRYSTAL_gc
	             | CLKCTRL_ENABLE_bm);

	/* Confirm crystal oscillator start-up */
	while(!(CLKCTRL.MCLKSTATUS & CLKCTRL_EXTS_bm))
	{
		;
	}

	/* Clear RUNSTDBY for power save during sleep */
	ccp_write_io((uint8_t *) &CLKCTRL.XOSCHFCTRLA, 
	             CLKCTRL.XOSCHFCTRLA & ~CLKCTRL_RUNSTDBY_bm);

Select XOSCHF as source by writing a ‘1’ to the SOURCE bit in the PLL Control A (CLKCTRL.PLLCTRLA) register, and select the multiplication factor by writing to the MULFAC bit field in the same register.

This register has Configuration Change Protection (CCP), so the ccp_write_io function in cpufunc.h should be used to ensure correct timing for the unlock of the register.

Figure 8-1. CLKCTRL.PLLCTRLA – Enable PLL with XOSCHF as source

	/* Set the PLL to use XOSCHF as source, and select 3x multiplication factor */
	ccp_write_io((uint8_t *) &CLKCTRL.PLLCTRLA, 
	             CLKCTRL_SOURCE_bm | CLKCTRL_MULFAC_3x_gc);

To select the PLL as clock source for TCD0, the PLL setting must be written to the Clock Select (CLKSEL) bit field in the Control A (TCD0.CTRLA) register.

Figure 8-3. TCD0.CTRLA – Enable TCD0 with PLL as source

	/* Configure the TCD with PLL (48 MHz) as source */
	TCD0.CTRLA = TCD_CLKSEL_PLL_gc | TCD_CNTPRES_DIV1_gc | TCD_SYNCPRES_DIV1_gc;

	/* Replace with your application configuration */

	/* Enable TCD0 */
	TCD0.CTRLA |= TCD_ENABLE_bm;

The code for this example is available in the TCD-with-XOSCHF-and-PLL folder in these github repositories: