5 Data and Results

The 40 kHz signal that is needed to drive the ultrasonic transducer is generated by the PWM1 peripheral and can be observed in Figure 5-1 in gray (PWM_DRIVE). The logic analyzer capture also shows the PWM2’s control signal in brown (PWM_CONTROL), that determines the measurement acquisition interval and number of pulses, the two resulting 180 degrees out-of-phase drive signals in red and orange (DRIVE1 and DRIVE2) and the inverted polarity PWM2’s delay signal in yellow (PWM_TIMER), which implements the hardware delay that avoids post-drive ringing.

Figure 5-1. Logic Analyzer Capture of the Drive and Control Signals

Figure 5-2 highlights a received amplified ultrasonic echo in gray (OPAMP_OUT) along with the two PWM2 signals. One can clearly see the hardware delay between the falling edge of the PWM_CONTROL (that starts the UTMR’s counting) and the rising edge of the PWM_TIMER (that enables the OPA’s amplification).

Figure 5-2. Logic Analyzer Capture of the Control Signals and the Amplified Ultrasonic Echo Waveform

Figure 5-3 illustrates the same scenario with the same signals, but with the OPA’s peak detector enabled. One should observe the small peak at the end of the main signal’s amplitude. This would have been detected as a new echo signal by the comparator if its interrupts hadn’t been disabled after the first acquisition in the current measurement window.

Figure 5-3. Logic Analyzer Capture of the Control Signals and the Peak of the Echo Waveform