3 Peripherals Used

The PWM peripheral provides a 16-bit Pulse-Width Modulator with various operating modes, a compare feature, and multiple outputs. The outputs are grouped into slices, with each slice having the same period. The duty cycle of these slices can be altered individually for each output.

In this application, PWM1 is configured to generate the 40 kHz drive signal. The PWM is set to use just a single output from its first slice at a fixed 50% duty cycle. The signal generated by the PWM represents the input for the Complementary Waveform Generator module. The PWM2 instance is used to generate two control signals using the two outputs of its first slice. The first output is used to set the duration of the generated pulses, by configuring the duty cycle, and the time between each measurement, by adjusting the period. This output represents one of the inputs to the Configurable Logic Cell and the control signal for the Universal Timer. The second output implements the hardware delay that avoids post-drive ringing. The duration of the delay is set by the duty cycle, which is always greater than the duty cycle of the pulse control signal. The oscillation dampening is effectively achieved by controlling the Operational Amplifier’s operating mode.

The Complementary Waveform Generator (CWG) module produces half-bridge, full-bridge, or steering of PWM waveforms. The CWG generates two output waveforms from the selected input source and the off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby creating a dead time. The CWG is configured to utilize the 40 kHz drive signal generated by the first PWM module as its input source. The Operating Output mode is set to Half Bridge, therefore the module converts the single input to two 180 degrees out-of-phase PWM signals, CWG1A and CWG1B. These signals serve as the other inputs to the CLC. As the ultrasonic transducer is not sensitive to same-time signal switching, consequently the dead time feature is disabled.

The Configurable Logic Cell module (CLC) provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 256 input signals and, through the use of configurable gates, it effectively reduces those inputs to four logic lines that drive one of eight selectable single-output logic functions.

In this project, the CLC makes use of two of its instances, CLC3 and CLC4, to apply an AND logic function between CWG1A and CWG1B, respectively, and the control signal from the PWM2 module. Therefore, the mode, or logic function, for the two instances is set to AND-OR. The two output pins of the module are connected externally to the transmitter transducer. One should observe the fact that, in this application, the CLC module behaves like an amplitude modulator, where the carrier signal is represented by one of the two 40 kHz signals and the message signal is characterized by the control signal generated by the PWM2 instance.

The Operational Amplifier module (OPA) features a standard general-purpose three-terminal device with programmable gain options, adjustable input offset voltage and hardware override control capabilities. The OPA is configured to function in the Inverting Programmable Gain Amplifier mode, therefore the output of the OPA is connected internally to the inverting input through the resistive ladder and OPA operates with an amplification determined by the resistors’ value. The OPA is configured to have the following resistor values: R1 = 1R and R2 = 15R, resulting in a gain of 15. The non-inverting input of the OPA is connected internally to V_DD/2 while the inverting input is connected externally to the receiver transducer through a coupling capacitor.

Throughout the application run time, the OPA is configured to operate as a peak detector, having a discharge capacitor connected to its output pin and ground the discharge time being dependent upon the values of the load resistance and the capacitance used. The output of the peak detector is connected externally to the pin corresponding to the inverting input of the Comparator (CMP) module. The application also makes use of the hardware override control feature by modifying the gain in accordance with the control signal generated by the second output of the PWM2 module. Therefore, when the signal is high, the OPA has the user-defined gain value (i.e. 15) and while the signal is low, the OPA switches to unity gain. This functionality is used to dampen the oscillation caused by post-drive ringing by not amplifying the signal during the hardware delay.

The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of V_DD, with 1.024V, 2.048V, or 4.096V as its selectable output levels. The output of the FVR can be configured to supply a reference voltage to analog peripherals such as ADC, CMP, and DAC. For this application, the FVR is configured to have a voltage reference of 2.048V and it is internally connected to the positive reference of the DAC.

The DAC supplies a variable voltage reference, ratiometric with the input source, with programmable selectable output levels. In this application, the DAC module behaves as a voltage reference for the Comparator (CMP) module and is connected internally to it. The DAC module sets the minimum threshold value for a received ultrasonic echo to be detected. The positive input reference is set to FVR, as mentioned previously, and the negative one is connected to V_SS.

Comparators (CMP) are used to interface analog circuits to digital circuits by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.

The CMP module has its positive input connected internally to the output of the DAC module, while the negative input is connected externally through a wire to the output of the peak detector. Furthermore, the CMP module has its interrupt enabled and an interrupt is triggered when the output value of the peak detector meets the required threshold value set by the DAC. Comparators are very useful in mixed signal applications, as they provide analog functionality interdependent of program execution.

The Universal Timer module (UTMR) is a 16-bit timer/counter with a combination of signal measurement and hardware limit timer functions. It is designed to provide all timer/counter-related functions in a single peripheral. The UTMR is configured to measure the time needed for the round trip of the ultrasonic signal. This is accomplished by setting the external reset input to be the PWM2 instance’s first output (i.e. the one that controls the two PWM drive signals) and setting up the following two options: the falling edge of the external input as a start condition and the reset condition triggered when the external reset signal is high. The actual measurement is acquired when the CMP module generates an interrupt prompting a capture command, followed by the computation of the traveled distance.

The Universal Asynchronous Receiver Transmitter (UART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer, independent of device program execution. The UART module is set to use the standard 8-N-1 configuration at a baud rate of 115200, while also enabling the use of printf as a means of transmitting strings to the serial bus. For the purposes of this project, the UART module is used to display information to the user, such as the distance measured.

The General-Purpose Input/Output (GPIO) system of the PIC18-Q71 serves as a way for the microcontroller to interact with the outside world through the use of external pins. The GPIO is structured into ports, each up to eight I/O pins. Each pin can be configured individually by setting different registers such as Data Direction, Output Latch, Analog Select, Weak Pull-Up, and others. This flexible configuration allows the user to set each pin to be an input or output, to modify their states and characteristics. This application makes use of the GPIO system to connect the two ultrasonic transducers to the microcontroller and to link the output of the peak detector to the inverting input of the comparator.