3 Module Overview
The Reset Controller contains an NRST Manager and a Reset State Manager. It runs at Slow Clock (SCLK) and generates the following:
Processor and Watchdog Timer reset
Embedded peripheral reset
Co-processor and Co-processor peripheral reset (SAM4C devices only)
External device reset (via the NRST pin)
These reset signals are asserted by the Reset Controller acting on external events or as the result of an action performed by software. The Reset State Manager controls the operation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required.