28.3.3 Analog Comparator Control and Status Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name: | ACSR |
Offset: | 0x50 |
Reset: | N/A |
Property: | When addressing as I/O Register: address offset is 0x30 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ACD | ACBG | ACO | ACI | ACIE | ACIC | ACIS [1:0] | |||
Access | R/W | R/W | R | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ACD Analog Comparator Disable
Bit 6 – ACBG Analog Comparator Bandgap Select
Bit 5 – ACO Analog Comparator Output
Bit 4 – ACI Analog Comparator Interrupt Flag
Bit 3 – ACIE Analog Comparator Interrupt Enable
Bit 2 – ACIC Analog Comparator Input Capture Enable
Bits 1:0 – ACIS [1:0] Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt.
ACIS1 | ACIS0 | Interrupt Mode |
---|---|---|
0 | 0 | Comparator Interrupt on Output Toggle. |
0 | 1 | Reserved |
1 | 0 | Comparator Interrupt on Falling Output Edge. |
1 | 1 | Comparator Interrupt on Rising Output Edge. |
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.