14.2.2 Clock Start-up Sequence

Any clock source needs a sufficient V_CC to start oscillating and a minimum number of oscillating cycles before it can be considered stable.

To ensure sufficient V_CC, the device issues an internal reset with a time-out delay (t_TOUT) after the device reset is released by all other reset sources. See the Related Links for a description of the start conditions for the internal reset. The delay (t_TOUT) is timed from the Watchdog Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in the Table below. The frequency of the Watchdog Oscillator is voltage dependent.

Main purpose of the delay is to keep the device in reset until it is supplied with minimum V_CC. The delay will not monitor the actual voltage, so it is required to select a delay longer than the V_CC rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure sufficient V_CC before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is not recommended.

The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.

The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from Power-save or Power-down mode, V_CC is assumed to be at a sufficient level and only the start-up time is included.