18.2.5 Pin Change Interrupt Flag
Register
When addressing I/O Registers as data space using LD
and ST instructions, the provided offset must be used. When using the I/O specific
commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset
within 0x00 - 0x3F.
| Name: | PCIFR |
| Offset: | 0x3B |
| Reset: | 0x00 |
| Property: | When addressing as I/O Register:
address offset is 0x1B |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | PCIF2 | PCIF1 | PCIF0 | |
| Access | | | | | | R/W | R/W | R/W | |
| Reset | | | | | | 0 | 0 | 0 | |
Bit 2 – PCIF2 Pin Change
Interrupt Flag 2
When a logic change
on any PCINT[23:16] pin triggers an interrupt request, PCIF2 will be set. If the
I-bit in SREG and the PCIE2 bit in PCICR are set, the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is
executed. Alternatively, the flag can be cleared by writing '1' to
it.
Bit 1 – PCIF1 Pin Change
Interrupt Flag 1
When a logic change
on any PCINT[14:8] pin triggers an interrupt request, PCIF1 will be set. If the
I-bit in SREG and the PCIE1 bit in PCICR are set, the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is
executed. Alternatively, the flag can be cleared by writing '1' to
it.
Bit 0 – PCIF0 Pin Change
Interrupt Flag 0
When a logic change
on any PCINT[7:0] pin triggers an interrupt request, PCIF0 will be set. If the I-bit
in SREG and the PCIE0 bit in PCICR are set, the MCU will jump to the corresponding
Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing '1' to it.
