7 Product Mapping and Peripheral Access

The following figure shows the default memory mapping of the Arm Cortex-M core.

SRAM1 shown in the mapping above is seen at the address 0x20080000 (through S-bus) from Core 0 side and at address 0x00000000 (through I/D Bus) from Core 1 side. Instruction fetch from Core 1 to the 0x20080000 SRAM1 address range is possible but leads to reduced performance due to the fact that instructions and read/write data go through the System Bus (S-Bus). Maximum performance for Core 1 (Metrology Core) is obtained by mapping the instruction code to the address 0x00000000 (SRAM1 through I/D-Code) and read/write data from the address 0x20088000 (SRAM2 through S-Bus). For Core 0 (Application Core), maximum performance is achieved when the instruction code is mapped to the Flash address and read/write data are mapped into SRAM0.

Memories and peripherals accessed by the cores are listed below:

• Core 0 (Application Core):
  • All internal memories
  • All internal peripherals
• Core 1 (Metrology/Coprocessor Core):
  • SRAM0/1/2 memories
  • All internal peripherals except where noted as “Core 0 only” in the tables above

If Core 1 is not used (clock stopped and reset active), all the peripherals, SRAM1 and SRAM2 of the Subsystem 1 can be used by the Application Core (Core 0) as long as the peripheral bus clock and reset are configured.

For detailed memory access versus Matrix hosts/clients, refer to the section Bus Matrix (MATRIX).