IEEE® 754-compliant, single-precision Floating
Point Unit (FPU), DSP instruction, Thumb®-2 instruction set
Up to 2 Mbytes of embedded dual plane/dual boot Flash
Built-in ECC,
Read-While-Write (RWW) support and Suspend/Resume of write/erase
operations
Endurance of 100K
Write/Erase cycles (1M in qualification)
Up to 512 Kbytes of embedded SRAM
Metrology/Coprocessor Core (CM4-C1)
Arm Cortex-M4F running at up to 240 MHz
IEEE 754-compliant, single-precision Floating Point Unit
(FPU), Memory Protection Unit, DSP instruction, Thumb-2 instruction set
32 Kbytes of embedded SRAM for program code (I-code bus)
and program data (D-code bus and system bus)
16 Kbytes of embedded SRAM for program data (system
bus)
Symmetrical/Asynchronous Dual Core Architecture
Interrupt-based inter-processor communication
Asynchronous clocking
One interrupt controller (NVIC) for each core
Energy Metering Analog
Front End (EMAFE)
Single-phase and dual-phase meter support
Compliant with electricity metering standards up to class
0.2 (ANSI C12.20-2002 and IEC 62053-22)
Works with Microchip IEC-compliant and ANSI-compliant
Metrology DSP Library
Five delta-sigma ADC measurement channels, 24-bit
resolution, 102 dB dynamic range
Current channels with pre-gain (x1, x2, x4, x8) support
directly connected shunt, current transformer and Rogowski coils sensors
without any active components
Dedicated current channel for neutral current measurement
(anti-tamper)
Precision voltage reference. Temperature drift: 10 ppm/°C
typical with software correction using factory-programmed calibration
registers
Dedicated 2.8V LDO regulator to supply the analog front
end
3.0V to 3.6V operation, ultra-low power: less than 2.5 mW
per channel at a 3.3V
Security and Cryptography
Secure Boot
Secure key storage and
transfer to Advanced Encryption Standard (AES) and AES Bridge (AESB) without
processor intervention
One-time programmable block for software monotonic counter
Security bit to disable debug port access
True Random Number Generator (TRNG)
Deterministic Random Number Generator (DRNG) support as required by NIST
800-90B
AES: 256-bit, 192-bit, 128-bit key algorithm, compliant
with FIPS PUB-197 specifications, ARIA
AES128 on-the-fly
encryption/decryption bridge for QSPI communications
Secure Hash Algorithm (SHA) supporting SHA1, SHA224,
SHA256, SHA384, and SHA512 compliant with FIPS PUB-197 specifications, and
associated HMAC
Classical Public Key Cryptographic Controller (CPKCC)
supporting:
RSA up to 7168 bits,
elliptic curve, DSA, DRNG
768 bits of General Purpose Backup Registers (GPBR) can be
defined as write-once
Automatic and immediate keys erasing upon detection of
Flash erase signal assertion
Erase of AES keys,
QSPI scrambling keys and GPBR
Anti-tamper with time-stamping, configurable and immediate
actions upon detection
Erase of AES, AESB
keys, QSPI scrambling keys and General Purpose Backup registers
Integrity Check Module (ICM) based on SHA256,
autonomous
Dual-Core Shared System Controller
Power supply
Embedded core and LCD
voltage regulator for single-supply operation
Supply monitors
Ultra-low-power
Backup mode
Clock
Programmable PLLs and
oscillator clock sources
Clock failure
detection
CPU frequency
monitor
Main crystal
oscillator failure detection
32.768 kHz crystal
oscillator frequency monitor and failure detection
Independent Dual
Watchdog Timer (DWDT)
12 MHz internal RC
oscillator
Ultra-low power Real-Time Clock (RTC) with Gregorian,
Persian calendars, and UTC mode, calibration circuitry to compensate the
32.768 kHz crystal drift with observability of compensated clock on output
pin
Peripheral and memory-to-memory DMA channels
Shared Peripherals
Segmented LCD Controller (SLCDC)
Static, ½, ⅓, and ¼
bias
Software-selectable
LCD output voltage (contrast)
Can be used in Backup
mode
Communication Interfaces
FLEXCOMs supporting UART/USART, SPI, TWI/I2C
with FIFOs
Metrology-specific
multi-channel SPI with legacy support
Metrology-specific two-wire UARTs supporting optical
transceiver providing an electrically-isolated serial communication with
hand-held equipment, such as calibrators, compliant with ANSI-C12.18 or
IEC62056-21 norms
3 x
24-bit resolution PWM-based metrology pulse outputs
Debugger Development Support
Arm CoreSight™ JTAG-DP or SW-DP debug port with dual-core star topology AHB-AP debug access port implementation
Debug synchronization between both cores
Wake-up from debug request
Unlimited software breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Analog Conversion Block
12-bit ADC module
1 Msps S/H ADC
Up to 8 channels
Two analog comparators
Temperature sensor
Closed-Circuit Voltage (CCV) measurement on battery voltage
input rail (VBAT)
Timers/Output Compare/Input Capture
12-channel 32-bit Timer Counters (TC) with Capture,
Waveform, Compare and basic PWM modes. Quadrature decoder logic and 2-bit
Gray up/down counter
3-channel, 24-bit PWM with complementary outputs, dead-time
generator, and external trigger modes
I/O
I/O lines with slew rate control to ease PCB design and EMC
compliance, external interrupt capability (edge or level sensitivity),
Schmitt trigger, internal pull-up/pull-down, debouncing, glitch filtering,
and on-die series resistor termination
Software and Tools Support
Microchip ANSI and IEC Metrology Compliant Library
Microchip Smart Energy
Framework Software Examples
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
