5 Interpreting the Fitter Report

The ATF15XX/ATF1500 fitter creates a report (log) file (*.fit) that documents the fitting process. This report file is created whether the design fits or not. If the design does not fit, the fitter reports errors in the logic file. If the design fits, a JEDEC (.JED) file is generated in addition to the report file. The Fitter Report contains the following sections:

  • Initial Fitting Strategy and Properties
  • Global Pin Assignments
  • Input/Output Pin Pre-assignments
  • Control Signal Patching
  • Floating (Unassigned) Signal Placement
  • Control Signal Assignment
  • Programmed Logic
  • Pin Layout and Listing
  • Logic Resources Usage

Figure 5-1 shows a sample ATF1502 fitter report for the CLOCK design example and provides descriptions of the various sections within the report.

Figure 5-1. Sample Fitter Report File for the CLOCK Design Example
Atmel ATF1502 Fitter Version 1918 ,running Thu Jun 12 13:35:07 2025

fit1502 C:\WinCUPL\Examples\New\CLOCK\CLOCK.tt2

-CUPL

-device PLCC44

-tech ATF1502AS

-JTAG OFF

This section shows the fitter option selected by the user.
****** Initial fitting strategy and property ******

Netlist_in_file = CLOCK.tt2

Netlist_out_file = CLOCK.tt3

Jedec_file = CLOCK.jed

Vector_file = CLOCK.tmv

verilog_file = CLOCK.vt

Log_file = CLOCK.fit

Device_name = PLCC44

Tech_name = ATF1502AS

Package_type = PLCC

Preassignment = try

Security_mode = OFF

Pin-Keeper = OFF

supporter = CUPL

optimize = ON

Xor_synthesis = OFF

Foldback_logic = OFF

Cascade_logic = OFF

Output_fast = ON

This section describes the initial fitting properties and strategies used by the fitter during the first attempt to fit the design. These options are either set by the user or set to the fitter’s default settings.
*************************************

Power down pin 1 = OFF

Power down pin 2 = OFF

power_reset = OFF

JTAG = OFF

TDI pullup = OFF

TMS pullup = OFF

MC_power = OFF

Open_collector = OFF

ITD0 = ON

ITD1 = ON

ITD2 = ON

Fast_inlatch = off

Latch_synthesis = off

Push_gate = on

Verilog_sim = off

VHDL_sim = off

Out_Edif = off

Logic Doubling = off

****** End of fitting strategy and property ******

---------------------------------------------------------

Fitter_Pass 1, Preassign = KEEP, LOGIC_DOUBLING : OFF

...

Performing global Output Enable pin assignments ...

Performing global pin assignments ...

The fitter keeps pre-assignments on the first design pass.
--------------------------------------
Final global control pins assignment (if applicable)...
-------------------------------------------------------

clk assigned to pin 43

Performing input pin pre-assignments ...

Final pin assignment for global clock input.
------------------------------------

clk assigned to pin 43

Attempt to place floating signals ...

Pin assignment for input pins.
------------------------------------

a is placed at pin 4 (MC 1)

b is placed at pin 5 (MC 2)

c is placed at pin 6 (MC 3)

clken is placed at pin 7 (MC 4)

y1 is placed at pin 14 (MC 10)

y0 is placed at pin 41 (MC 17)

y2 is placed at pin 24 (MC 32)

Pin assignment for I/O pins and macrocell assignments for buried nodes.
Pin layout diagram.

VCC = Supply Voltage pin for the device core

GND = GND pin which must be connected to ground

NC = Unused I/O pins which must be unconnected on the board

Universal-Interconnect-Multiplexer assignments

Universal Interconnect Multiplexer (UIM) assignments for the various Logic Array Blocks (LABs).
------------------------------------------------

FanIn assignment for block A [3]

{

a,

b,

c,

}

Multiplexer assignment for block A

b (MC1 P) : MUX 11 Ref (A2p)

a (MC2 P) : MUX 12 Ref (A1p)

c (MC3 P) : MUX 14 Ref (A3p)

FanIn assignment for block B [3]

{

a,

b,

clken,

}

Multiplexer assignment for block B

b (MC1 P) : MUX 11 Ref (A2p)

clken (MC3 P) : MUX 12 Ref (A4p)

a (MC2 P) : MUX 15 Ref (A1p)

Creating JEDEC file C:\WinCUPL\Examples\New\CLOCK\CLOCK.jed ...

PLCC44 programmed logic:

The fitter generates a JEDEC (.JED) file if the design fits successfully.
-----------------------------------

y1.D = !b;

y0.D = b;

y2.D = b;

y1.C = (!a & c);

y0.C = clk;

y2.C = clk;

y2.AR = a;

y2.CE = clken;

PLCC44 Pin/Node Placement:

This section shows all logic equations implemented in the target device.
-----------------------------------

Pin 4 = a; /* MC 1 */

Pin 5 = b; /* MC 2 */

Pin 6 = c; /* MC 3 */

Pin 7 = clken; /* MC 4 */

Pin 14 = y1; /* MC 10 */

Pin 24 = y2; /* MC 32 */

Pin 41 = y0; /* MC 17 */

Pin 43 = clk;

** Resource Usage **

DCERP Field = Summary of Allocations.

|||||

|||||_Preset [p,-] == p = PT preset, - No Preset.

||||

||||__Reset [g,r,-] == g= Global AR, r = PT reset, - No reset.

|||

|||___Clock Enable [e,-] == e = Product Term, - always enabled.

||

||____Clock [c,g,-], == c = Product term, g = Global term, - No Clock.

|

|_____Type [C,D,L,T], == Register type C= combin, D=dff, L=latch, T=tff.

For input only = INPUT.

This section shows all final input and I/O pin assignments.

SO Pin Options Field = Summary of Allocations.

||

||_OpenCol [o,-] == o = Open Collector enabled, - CMOS drive.

|

|__Slew [s,f] == Output Slew/Drive rate, s = slow/low, f = fast/hi drive.

This section lists all resources available in the target device and describes the mapping of the design logic into the ATF15XX device.

MCell Pin# Oe PinDrive DCERP FBDrive DCERP Foldback CascadeOut TotPT SO

MC1 4 -- a INPUT -- -- -- 0 f-

MC2 5 -- b INPUT -- -- -- 0 f-

MC3 6 -- c INPUT -- -- -- 0 f-

MC4 7 -- clken INPUT -- -- -- 0 f-

MC5 8 -- -- -- -- 0 f-

MC6 9 -- -- -- -- 0 f-

MC7 11 -- -- -- -- 0 f-

MC8 12 -- -- -- -- 0 f-

MC9 13 -- -- -- -- 0 f-

MC10 14 on y1 Dc--- -- -- -- 2 f-

MC11 16 -- -- -- -- 0 f-

MC12 17 -- -- -- -- 0 f-

MC13 18 -- -- -- -- 0 f-

MC14 19 -- -- -- -- 0 f-

MC15 20 -- -- -- -- 0 f-

MC16 21 -- -- -- -- 0 f-

MC17 41 on y0 Dg--- -- -- -- 1 f-

MC18 40 -- -- -- -- 0 f-

MC19 39 -- -- -- -- 0 f-

MC20 38 -- -- -- -- 0 f-

MC21 37 -- -- -- -- 0 f-

MC22 36 -- -- -- -- 0 f-

MC23 34 -- -- -- -- 0 f-

MC24 33 -- -- -- -- 0 f-

MC25 32 -- -- -- -- 0 f-

MC26 31 -- -- -- -- 0 f-

MC27 29 -- -- -- -- 0 f-

MC28 28 -- -- -- -- 0 f-

MC29 27 -- -- -- -- 0 f-

MC30 26 -- -- -- -- 0 f-

MC31 25 -- -- -- -- 0 f-

MC32 24 on y2 Dger- -- -- -- 3 f-

MC0 2 -- -- -- -- 0 f-

MC0 1 -- -- -- -- 0 f-

MC0 44 -- -- -- -- 0 f-

MC0 43 clk INPUT -- -- -- 0 f-

Logic Array Block Macro Cells I/O Pins Foldbacks TotalPT FanIN Cascades

A: MC1 - MC16 1/16(6%) 5/16(31%) 0/16(0%) 2/80(2%) 3/40(7%) 0

B: MC17 - MC32 2/16(12%) 2/16(12%) 0/16(0%) 4/80(5%) 3/40(7%) 0

Total dedicated input used: 1/4 (25%)

Total I/O pins used 7/32 (21%)

Total Macro cells used 3/32 (9%)

Total Flip-Flop used 3/32 (9%)

Total Foldback logic used 0/32 (0%)

Total Nodes+FB/MCells 3/32 (9%)

Total cascade used 0

Total input pins 5

Total output pins 3

Total Pts 6

This section summarizes total macrocell and logic resource utilization by the logic design.

Creating pla file C:\WinCUPL\Examples\New\CLOCK\CLOCK.tt3 with 0 inputs 0 outputs, 0 pins 0 nodes and 0 pterms...

---------------- End fitter, Design FITS

$Device PLCC44 fits; JTAG OFF; Secure OFF

FIT1502 completed in 0.00 seconds