11.4.2 Natural Order (Hardware) Priority

When vectored interrupts are enabled and more than one interrupt with the same user specified priority level is requested, the priority conflict is resolved by using a method called “Natural Order Priority”. Natural order priority is a fixed priority scheme that is based on the IVT.

Table 11-2. Interrupt Vector Priority Table
Vector

Number

Interrupt

source

Vector

Number

(cont.)

Interrupt

source

(cont.)

0x0 Software Interrupt 0x2E PWM2RINT
0x1 HLVD (High/Low-Voltage Detect) 0x2F PWM2GINT
0x2 OSF (Oscillator Fail) 0x30 INT1
0x3 CSW (Clock Switching) 0x31 CLC7
0x4 NVM 0x32 CWG1 (Complementary Waveform Generator)
0x5 CLC1 (Configurable Logic Cell) 0x33 NCO1 (Numerically Controlled Oscillator)
0x6 CRC (Cyclic Redundancy Check) 0x34 DMA2SCNT
0x7 IOC (Interrupt-On-Change) 0x35 DMA2DCNT
0x8 INT0 0x36 DMA2OR
0x9 ADTIE (ADC Threshold Interrupt) 0x37 DMA2A
0xA AD (ADC Conversion Complete) 0x38 I2C1RX
0xB ACT (Active Clock Tuning) 0x39 I2C1TX
0xC I2C2RX 0x3A I2C1
0xD I2C2TX 0x3B I2C1E
0xE I2C2 0x3C -
0xF I2C2E 0x3D CLC3
0x10 ZCD2 (Zero-Cross Detection) 0x3E PWM3RINT
0x11 CLC5 0x3F PWM3GINT
0x12 IOCSR (Interrupt-On-Change Signal Routing Ports) 0x40 U2RX
0x13 ZCD1 (Zero-Cross Detection) 0x41 U2TX
0x14 DMA1SCNT (Direct Memory Access) 0x42 U2E
0x15 DMA1DCNT 0x43 U2
0x16 DMA1OR 0x44 -
0x17 DMA1A 0x45 CLC4
0x18 SPI1RX (Serial Peripheral Interface) 0x46 CCP2 (Capture/Compare/PWM)
0x19 SPI1TX 0x47 SCAN
0x1A SPI1 0x48 CM1 (Comparator)
0x1B TMR2 0x49 - 0x4B -
0x1C TMR1 0x4C DMA3SCNT
0x1D TMR1G 0x4D DMA3DCNT
0x1E CCP1 (Capture/Compare/PWM) 0x4E DMA3OR
0x1F TMR0 0x4F DMA3A
0x20 U1RX 0x50 INT2
0x21 U1TX 0x51 CLC8
0x22 U1E 0x52 TU16B (Universal Timer 16B)
0x23 U1 0x53 TMR4
0x24 TMR3 0x54 DMA4SCNT
0x25 TMR3G 0x55 DMA4DCNT
0x26 PWM1RINT 0x56 DMA4OR
0x27 PWM1GINT 0x57 DMA4A
0x28 - 0x58 SPI2RX (Serial Peripheral Interface)
0x29 CLC6 0x59 SPI2TX
0x2A TU16A (Universal Timer 16A) 0x5A SPI2
0x2B TMR6 0x5B VDDIO2LVDIF
0x2C CM2 (Comparator) 0x5C VDDIO2RDYIF
0x2D CLC2 0x5D VDDIO2PORIF

The natural order priority scheme goes from high-to-low with increasing vector numbers, with 0 being the highest priority and decreasing from there.

For example, when two concurrently occurring interrupt sources that are both designated high priority, using the IPRx register will be resolved using the natural order priority (i.e., the interrupt with a lower corresponding vector number will preempt the interrupt with the higher vector number).

The ability for the user to assign every interrupt source to high- or low-priority levels means that the user program can give an interrupt with a low natural priority, a higher overall priority level.