41.5.17 ADACC

ADC Accumulator Register⁽¹⁾

See the “Computation Operation” section for more details.

Important: This register contains signed two’s complement accumulator value and the upper unused bits contain copies of the sign bit.

Note:

This register can only be written when GO = 0.
The individual bytes in this multibyte register can be accessed with the following register names when applicable. The size of this multibyte register may vary depending on the device family. Refer to the register summary for more information about the implemented bit width of this register.
- ADACCH: Accesses the high byte ADACC[15:8]
- ADACCL: Accesses the low byte ADACC[7:0]

Name:	ADACC
Address:	0x3E3


Bit	15	14	13	12	11	10	9	8
	ACC[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	x	x	x	x	x	x	x	x


Bit	7	6	5	4	3	2	1	0
	ACC[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	x	x	x	x	x	x	x	x

Bits 15:0 – ACC[15:0] ADC Accumulator - Signed two’s complement

This register can only be written when GO = 0. The individual bytes in this multibyte register can be accessed with the following register names when applicable. The size of this multibyte register may vary depending on the device family. Refer to the register summary for more information about the implemented bit width of this register. ADACCH: Accesses the high byte ADACC[15:8] ADACCL: Accesses the low byte ADACC[7:0]