48.3.4 I/O Ports

Table 48-4. 
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym. Device Characteristics Min. Typ.† Max. Units Conditions
Input Low Voltage
VIL I/O PORT:
D300
  • with LVBUF (TTL compatible)
 — — 0.9 V
D302
  • with Schmitt Trigger buffer
 — — 0.2 VDD V 2.0V ≤ VDD ≤ 5.5V
— — 0.2 VDDIOx V 2.0V ≤ VDDIOx ≤ 5.5V
D303
  • with I2C levels
 — — 0.3 VDD V 2.0V ≤ VDD ≤ 5.5V
D304
  • with SMBus 2.0
 — — 0.8 V 2.7V ≤ VDD ≤ 5.5V
D305
  • with SMBus 3.0
 — — 0.8 V
D306 MCLR — — 0.2 VDD V
High Low Voltage
VIH I/O PORT:
D320
  • with LVBUF (TTL compatible)
 1.3 — — V
D322
  • with Schmitt Trigger buffer
 0.8 VDD — — V 2.0V ≤ VDD ≤ 5.5V
0.8 VDDIOx — — V 2.0V ≤ VDDIOx ≤ 5.5V
D323
  • with I2C levels
 0.7 VDD — — V
D324
  • with SMBus 2.0
 2.1 — — V 2.7V ≤ VDD ≤ 5.5V; 2.7V ≤ VDDIOx ≤ 5.5V
D325
  • with SMBus 3.0
 1.35 — — V
D326 MCLR 0.7 VDD — — V
Input Leakage Current(1)
D340 IIL I/O pins on VDD domain — ±5 ±125 nA

VSS ≤ VPIN ≤ VDD (VDD domain);

Pin at high-impedance, 85°C
D340A I/O pins on MVIO domain — ±5 ±125 nA VSS ≤ VPIN ≤ +6V (MVIO domain);

Pin at high-impedance, 85°C
D341 I/O pins on VDD domain — ±5 ±1000 nA

VSS ≤ VPIN ≤ VDD (VDD domain);

Pin at high-impedance, 125°C
D341A I/O pins on MVIO domain — ±5 ±1000 nA VSS ≤ VPIN ≤ +6V (MVIO domain);

Pin at high-impedance, 125°C
D342 MCLR(2) — ±50 ±200 nA VSS ≤ VPIN ≤ VDD,

Pin at high-impedance, 85°C
Weak Pull-up Current
D350 IPUR 80 140 200 μA VDD = 3.0V,

VPIN = VSS
Output Low Voltage
D360 VOL
  • with GPIO driver (all pins on VDD and MVIO domains)
 — — 0.6 V IOL = 10.0 mA,

VPIN = 3.0V
Output High Voltage
D370 VOH
  • with GPIO driver (all pins on VDD and MVIO domains)
 VDD - 0.7 — — V VPIN = 3.0V;

IOH = 6 mA
VDDIOx - 0.7 — — V
Load Capacitance
D380 CIO All I/O Pins (VDD and MVIO domains) — 5 50 pF
Input Capacitance
D390 CI All I/O Pins (VDD and MVIO domains) — — 5 pF

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. Negative current is defined as current sourced by the pin.
  2. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.