45.6.8 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read.

The following bits are synchronized when written:

The Software Reset bit in the Control A register (CTRLA.SWRST)
The Enable bit in the Control A register (CTRLA.ENABLE)

The following registers are synchronized when written:

The Input Control register (INPUTCTRL)
The Control B register (CTRLB)
The Reference Control (REFCTRL)
The Average control register (AVGCTRL)
The Sampling time control register (SAMPCTRL)
The Window Monitor Lower Threshold register (WINLT)
The Window Monitor Upper Threshold register (WINUT)
The Gain correction register (GAINCORR)
The Offset Correction register (OFFSETCORR)
The Software Trigger register (SWTRIG)

Required write synchronization is denoted by the "Write-Synchronized" property in the register description.

DS60001507N

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