1.5 Changing Channel or Reference Selection

The Analog Channel Selection and Reference Selection bit groups in the ADC Multiplexer Selection register (ADMUX.MUX and ADMUX.REFS) are buffered through a temporary register to which the CPU has random access.

If auto trigger mode is used, then ADMUX can be safely updated:
  • when the ADC Auto Trigger bit or ADC Enable bit in the ADC Control and Status A register (ADCSRA.ADATE or ADCSRA.ADEN) is cleared
  • or, during conversion, minimum one ADC clock cycle after the trigger event
  • or, after a conversion, before the ADC Interrupt Flag bit in ADCSRA (ADCSRA.ADIF) used as trigger source is cleared

By doing this, the new settings will affect the next ADC conversion.

In single conversion mode, the channel must be selected before starting the conversion. It is recommended to wait until the conversion completes before changing the channel, which will take effect one clock cycle after writing the ADC Start Conversion bit in ADCSRA (ADCSRA.ADSC) to '1'.

In free-running mode, the channel must be selected before starting the conversion. However, it is recommended to wait until the first conversion is completed before changing the channel, which will take effect one clock cycle after writing the ADC Start Conversion bit in ADCSRA (ADCSRA.ADSC) to '1'. But, since the next conversion has already started automatically, the changes will be reflected in the next following conversion.