1.1 ADC Operation

To make use of the ADC, the Power Reduction ADC bit in the Power Reduction register (PRR.PRADC) must be written to '0'. The ADC module must be disabled before PRR.PRADC can be written to '0'. The ADC module converts the analog input voltage to a 10-bit digital value. The minimum value represents GND and the maximum value denotes the reference voltage used. The reference voltage is chosen by the Reference Selection bit group in the ADC Multiplexer Selection register (ADMUX.REFS).

The analog input channel for conversion is selected by writing the appropriate value to the Analog Channel Selection bit group in ADMUX (ADMUX.MUX). This includes the ADC input pins along with internal voltage from the temperature sensor, GND, and the fixed bandgap reference voltage. To enable the ADC, the ADC Enable bit in the ADC Control and Status A register (ADCSR.ADEN) must be written to '1'. The channels selected for conversion will not go into effect until ADCSR.ADEN is written to '1'. Before entering Sleep mode, the ADC module can be disabled by writing ADCSR.ADEN to '0'. This reduces the power consumption caused by ADC.

Note: Refer to the device data sheet for details on voltage references and input channels available for the different megaAVR devices.

The 10-bit digital value after conversion is stored in ADCH and ADCL. ADCH holds the higher byte and ADCL holds the lower byte. Optionally, left adjustment of the result can be done by setting the ADLAR bit in the ADMUX register if necessary. If ADLAR is enabled and the application needs only 8-bit accuracy then ADCH alone can be read. Otherwise, ADCL must be read first followed by ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Access to ADC is blocked once ADCL is read. It is re-enabled only after ADCH is read.

The ADC module has one interrupt, which is triggered once a conversion is complete. If an interrupt occurs between reading ADCL and ADCH, it will get triggered and the result will be lost.

The figure below shows the block diagram of the ADC in the megaAVR devices.
Note: Dependent on the feature set of the different megaAVR devices, there might be some variations to the block diagram. Refer to the device data sheet for further information.
Figure 1-1. Analog to Digital Converter Block Diagram