| E | 09/2021 |
|
| D | 05/2021 |
- Added silicon revision B
- Added errata:
- CCL:
The CCL Must be Disabled to Change the
Configuration of a Single LUT
- TCA:
Restart Will Reset Counter Direction in NORMAL
and FRQ Mode
- TCB:
CCMP and CNT Registers Operate as 16-Bit
Registers in 8-Bit PWM Mode
- TCD:
- Asynchronous Input Events Not Working When TCD
Counter Prescaler is Used
- Halting TCD and Wait for SW Restart Does Not
Work if Compare Value A is ‘
0’
or Dual Slope Mode is Used
- Updated errata:
- RTC:
Any Write to the RTC.CTRLA Register Resets the
RTC and PIT Prescaler
- TWI:
TIMEOUT Bits in the TWI.MCTRLA Register are Not
Accessible
- Added data sheet clarifications:
- Memories:
Fuses - Factory Default Values
- SLPCTRL:
Sleep Mode Activity Overview
- USART:
TXDATA Buffer
- Package
Drawings:
- Package Marking Information
- Package Drawings
|
| C | 06/2020 |
- Added errata:
- Device:
- Writing the OSCLOCK Fuse in Fuse.OSCCFG to
‘1’ Prevents Automatic Loading of
Calibration Fuses
- USART:
- Full Range Duty Cycle Not Supported When
Validating LIN Sync Field
- Open-Drain Mode Does Not Work When TXD is
Configured as Output
- Added clarification for electrical characteristics for AC
peripheral
|
| B | 10/2019 |
- Updated document
template
- Updated errata
2.4.3 ADC Functionality
- Added
clarification for ADCn.CALIB.DUTYCYC register description
- Added
clarification for electrical characteristics of ADC and PTC
peripheral
|
| A | 06/2019 | Initial document release |
