4.2.1 Xplained Pro Extension Headers
The SAM C21 Xplained Pro headers EXT1, EXT2, and EXT3 offers access to the I/O of the microcontroller in order to expand the board e.g. by connecting extensions to the board. These headers are based on the standard extension header specified in Xplained Pro Standard Extension Header. The headers have a pitch of 2.54mm.
Pin on EXT1 | SAM C21 pin | Function | Shared functionality |
---|---|---|---|
1 [ID] | - | - | Communication line to the ID chip on an extension board. |
2 [GND] | - | - | Ground. |
3 [ADC(+)] | PB09 | INP1 | Shield |
4 [ADC(-)] | PB08 | INN1 | Shield |
5 [GPIO1] | PA20 | GPIO | Shield |
6 [GPIO2] | PA21 | GPIO | Shield |
7 [PWM(+)] | PB12 | TC0/WO0 | Shield and EDBG GPIO0 |
8 [PWM(-)] | PB13 | TC0/WO1 | Shield |
9 [IRQ/GPIO] | PB14 | IRQ14/GPIO | - |
10 [SPI_SS_B/GPIO] | PB15 | GPIO | - |
11 [TWI_SDA] | PA12 | SERCOM2 PAD[0] I2C SDA | EXT2, EXT3, Shield, Crypto Device, and EDBG I2C |
12 [TWI_SCL] | PA13 | SERCOM2 PAD[1] I2C SCL | EXT2, EXT3, Shield, Crypto Device, and EDBG I2C |
13 [USART_RX] | PA23 | SERCOM3 PAD[1] UART RX | EXT2, EXT3, and Shield |
14 [USART_TX] | PA22 | SERCOM3 PAD[0] UART TX | EXT2, EXT3, and Shield |
15 [SPI_SS_A] | PA17 | SERCOM1 PAD[1] SPI SS | - |
16 [SPI_MOSI] | PA18 | SERCOM1 PAD[2] SPI MOSI | - |
17 [SPI_MISO] | PA16 | SERCOM1 PAD[0] SPI MISO | - |
18 [SPI_SCK] | PA19 | SERCOM1 PAD[3] SPI SCK | - |
19 [GND] | - | - | Ground. |
20 [VCC] | - | - | Power for extension board. |
Pin on EXT2 | SAM C21 pin | Function | Shared functionality |
---|---|---|---|
1 [ID] | - | - | Communication line to the ID chip on an extension board. |
2 [GND] | - | - | Ground. |
3 [ADC(+)] | PA08 | AIN10 | Shield |
4 [ADC(-)] | PA09 | AIN11 | Shield |
5 [GPIO1] | PA10 | GPIO | - |
6 [GPIO2] | PA11 | GPIO | - |
7 [PWM(+)] | PB30 | TCC0/WO0 | Shield |
8 [PWM(-)] | PB31 | TCC0/WO1 | Shield |
9 [IRQ/GPIO] | PB16 | IRQ0/GPIO | EDBG GPIO1 |
10 [SPI_SS_B/GPIO] | PB17 | GPIO | EDBG GPIO2 |
11 [TWI_SDA] | PA12 | SERCOM2 PAD[0] I2C SDA | EXT1, EXT3, Shield, Crypto Device, and EDBG I2C |
12 [TWI_SCL] | PA13 | SERCOM2 PAD[1] I2C SCL | EXT1, EXT3, Shield, Crypto Device, and EDBG I2C |
13 [USART_RX] | PA23 | SERCOM3 PAD[1] UART RX | EXT1, EXT3, and Shield |
14 [USART_TX] | PA22 | SERCOM3 PAD[0] UART TX | EXT1, EXT3, and Shield |
15 [SPI_SS_A] | PB03 | SERCOM5 PAD[1] SPI SS | |
16 [SPI_MOSI] | PB00 | SERCOM5 PAD[2] SPI MOSI | EXT3, Shield, Shield(2), and EDBG SPI |
17 [SPI_MISO] | PB02 | SERCOM5 PAD[0] SPI MISO | EXT3, Shield, Shield(2), and EDBG SPI |
18 [SPI_SCK] | PB01 | SERCOM5 PAD[3] SPI SCK | EXT3, Shield, Shield(2), and EDBG SPI |
19 [GND] | - | - | Ground. |
20 [VCC] | - | - | Power for extension board. |
Pin on EXT3 | SAM C21 pin | Function | Shared functionality |
---|---|---|---|
1 [ID] | - | - | Communication line to the ID chip on an extension board. |
2 [GND] | - | - | Ground. |
3 [ADC(+)] | PB07 | AIN9/INP2 | Shield |
4 [ADC(-)] | PB06 | AIN8/INN2 | Shield |
5 [GPIO1] | PB04 | GPIO | Shield |
6 [GPIO2] | PB05 | GPIO | Shield |
7 [PWM(+)] | PA14 | TC4/WO0 | Crystal footprint |
8 [PWM(-)] | PA15 | TC4/WO1 | User LED and Crystal footprint |
9 [IRQ/GPIO] | PA28 | IRQ8/GPIO | User Button and EDBG GPIO3 |
10 [SPI_SS_B/GPIO] | PA27 | GPIO | Shield |
11 [TWI_SDA] | PA12 | SERCOM2 PAD[0] I2C SDA | EXT1, EXT2, Shield, Crypto Device, and EDBG I2C |
12 [TWI_SCL] | PA13 | SERCOM2 PAD[1] I2C SCL | EXT1, EXT2, Shield, Crypto Device, and EDBG I2C |
13 [USART_RX] | PA23 | SERCOM3 PAD[1] UART RX | EXT1, EXT2, and Shield |
14 [USART_TX] | PA22 | SERCOM3 PAD[0] UART TX | EXT1, EXT2, and Shield |
15 [SPI_SS_A] | PA02 | GPIO | DAC Header |
16 [SPI_MOSI] | PB00 | SERCOM5 PAD[2] SPI MOSI | EXT2, Shield, Shield(2), and EDBG SPI |
17 [SPI_MISO] | PB02 | SERCOM5 PAD[0] SPI MISO | EXT2, Shield, Shield(2), and EDBG SPI |
18 [SPI_SCK] | PB01 | SERCOM5 PAD[3] SPI SCK | EXT2, Shield, Shield(2), and EDBG SPI |
19 [GND] | - | - | Ground. |
20 [VCC] | - | - | Power for extension board. |