Introduction

Block Flow is a bottom-up design methodology that enables you to use design blocks (“components” in generic terms) as building blocks for your top-level design. These building blocks may have already completed layout and been optimized for timing and power performance for a specific Microchip device. Using these blocks as part of your top-level design can cut down design time as well as improve timing and power performance. Using blocks has the following advantages:

• Helps you focus on the timing of critical blocks and ensure the timing across the blocks meets requirements before proceeding to integrate your blocks at the top-level.
• Helps re-using blocks without re-optimization for timing closure; changes in other blocks have no impacts.
• Helps re-using blocks in multiple designs.
• Allows shorter verification time.

Blocks can be used in the following scenarios:

• You have multiple team members working on different parts of the same design.
• The design is congested (uses 90% or more of the resources on a given die).
• You have difficulty in meeting timing by doing the design in its entirety. Blocks enable you to compartmentalize the design and optimize sections before you optimize the entire design.
• You want to re-use some elements of your design.
• You want to use the identical elements multiple times in a single design.
• You want to make small changes in your design and expect to keep most of the design unchanged with ensured performance.

You cannot use blocks with all families, they are family and die specific. If your block has I/Os, it is also package specific.