Jump to main content
Classical Constraint Flow for SmartFusion® 2, IGLOO® 2, and RTG4™ Devices
Search
Introduction
Features
1
Creating Blocks - Options and Settings
1.1
Synthesis Tool Settings
1.2
Compile
1.3
Guidelines for Creating Blocks
2
Instantiating Blocks in your Top-Level Design
2.1
Import the Block
2.2
Create a Top-Level Design that Uses Blocks
3
Publishing Blocks After Compile or Layout
3.1
Publish After Compile
3.2
Publish After Layout
3.3
Published Content
4
Hierarchical Structure Resolution in Top-Level Projects
4.1
Duplicate Block Definition
4.2
Conflicting Definitions in top.v and Your Imported Block File
4.3
Resolving top.v and Block Instantiations
5
EDIF Netlist in the Top-Level Design
6
Synthesis
7
Resolving Place and Route Conflicts
7.1
Resolving Place and Route Conflicts in Compile
7.2
Compile - SmartFusion2, IGLOO2, and RTG4
8
Block PDC Commands
8.1
move_block
8.2
set_block_options
9
Publish Block - Configuration Options
9.1
Publish Block Configuration
9.2
Publish Options/Settings
10
Revision History
Microchip FPGA Support
Microchip Information
The Microchip Website
Product Change Notification Service
Customer Support
Microchip Devices Code Protection Feature
Legal Notice
Trademarks
Quality Management System
Worldwide Sales and Service
