SR Latch

This section describes an application example that uses CCL combinational and sequential logic to implement an SR latch. This functionality can be created using two adjacent LUTs (LUT0 and LUT1) connected through a sequential logic block.

Figure 1. Using CCL to Implement an SR Latch

For Set and Reset signals, two pins are used as inputs for LUTs (I/O PORT pin PA1 and I/O PORT pin PC1). That translates to the following code.

CCL.LUT0CTRLB = CCL_INSEL0_MASK_gc | CCL_INSEL1_IO_gc;	
CCL.LUT0CTRLC = CCL_INSEL2_MASK_gc;
CCL.LUT1CTRLB = CCL_INSEL0_MASK_gc | CCL_INSEL1_IO_gc;	
CCL.LUT0CTRLC = CCL_INSEL2_MASK_gc;

In this case, only the input selected for the Input signal needs to be considered when configuring the Truth register for each LUT. For instance, if the signal is active-high and available on LUTn_IN[1], the Truth register will be set to 0x02. If the input signal is active-low, which is the case for many evaluation kits, the Truth register will be set to 0x01. For the selected example, the input signals are active-low, so the Truth register will be set to 0x01 for both LUTs.

CCL.TRUTH0 = 0x01;
CCL.TRUTH1 = 0x01;

The truth table output is a combinatorial function of the inputs. This may cause some short glitches when the inputs change value. These glitches may not cause any problems, but if the LUT output is set to trigger an event, used as input on a timer or similar, an unwanted glitch may trigger unwanted events and peripheral action. In removing these glitches by clocking through the filters, the user will only get the intended output. Each Look-up Table (LUT) in the CCL includes a filter that can be used to synchronize or filter the LUT output.

Figure 2. CCL Filter

The selection of the filter option is done by using the FILTSEL[1:0] bits from the LUTnCTRLA register.

Figure 3. CCL Filter Options

CCL.LUT0CTRLA = CCL_FILTSEL_FILTER_gc;
CCL.LUT1CTRLA = CCL_FILTSEL_FILTER_gc;

The next step is to connect the LUTs through a sequential logic to create SR latch functionality. The bits in SEQSEL0[3:0] from the Sequential Control (SEQCTRL0) register select the sequential configuration for LUT0 and LUT1.

Figure 4. Sequential 1 Control 0 Register

This translates to the following code:

CCL.SEQCTRL0 = CCL_SEQSEL0_RS_gc;

To complete the setup and enable the LUT0 output on the LUT0OUT pin (PA3), the used LUTs and CCL need to be enabled.

CCL.LUT1CTRLA |= CCL_ENABLE_bm;
CCL.LUT0CTRLA |= CCL_ENABLE_bm | CCL_OUTEN_bm;
CCL.CTRLA = CCL_ENABLE_bm;

Tip: The full code example is also available in the Appendix section.

An MCC generated code example for AVR128DA48, with the same functionality as the one described in this section, can be found here: