Appendix

Logic AND Gate Code Example

#include <avr/io.h>

void PORT_init (void);
void CCL_init(void);

/**
 * \brief Initialize ports
 */
void PORT_init (void)
{
    PORTC.DIR &= ~PIN0_bm;         //PC0 - LUT1 IN[0]
    PORTC.DIR &= ~PIN1_bm;         //PC1 - LUT1 IN[1]
    PORTC.DIR &= ~PIN2_bm;         //PC2 - LUT1 IN[2]

    PORTC.DIR |= PIN3_bm;		   //PC3 - LUT1 output
}

/**
 * \brief Initialize CCL peripheral
 */
void CCL_init(void)
{

//configure inputs for used LUTs
    CCL.LUT1CTRLB = CCL_INSEL0_IO_gc    /* IO pin LUTn-IN0 input source */
                    | CCL_INSEL1_IO_gc; /* IO pin LUTn-IN1 input source */
    CCL.LUT1CTRLC = CCL_INSEL2_IO_gc;   /* IO pin LUTn-IN2 input source */
	
//Configure Truth Table
    CCL.TRUTH1 = 0x80; /* Truth 1: 128 */
	
//Enable LUT0 output on IO pin
    CCL.LUT1CTRLA = CCL_OUTEN_bm;     /* Output Enable: enabled */

//Enable LUTs
    CCL.LUT1CTRLA |= CCL_ENABLE_bm;    /* LUT Enable: enabled */
	
//Enable CCL module
    CCL.CTRLA = CCL_ENABLE_bm;         /* Enable: enabled */
}


int main(void)
{
    PORT_init();
    CCL_init();
    while (1) 
    {
        ;		
    }
}

State Decoder Code Example

#include <avr/io.h>

void PORT_init (void);
void CCL_init(void);

/**
 * \brief Initialize ports
 */
void PORT_init (void)
{

    PORTA.DIR &= ~PIN0_bm;         //PA0 - LUT0 IN[0]
    PORTA.DIR &= ~PIN1_bm;         //PA1 - LUT0 IN[1]
    PORTC.DIR &= ~PIN0_bm;         //PC0 - LUT1 IN[0]
    PORTC.DIR &= ~PIN1_bm;         //PC0 - LUT1 IN[1]
    PORTC.DIR &= ~PIN2_bm;         //PC0 - LUT1 IN[2]

    PORTA.DIR |= PIN3_bm;	        //PA3 - LUT0 output
 
}

/**
 * \brief Initialize CCL peripheral
 */
void CCL_init(void)
{

//configure inputs for used LUTs
    CCL.LUT0CTRLB = CCL_INSEL0_IO_gc    /* IO pin LUTn-IN0 input source */
                    | CCL_INSEL1_IO_gc; /* IO pin LUTn-IN1 input source */
    CCL.LUT0CTRLC = CCL_INSEL2_LINK_gc; /* Linked LUT input source */

    CCL.LUT1CTRLB = CCL_INSEL0_IO_gc    /* IO pin LUTn-IN0 input source */
                    | CCL_INSEL1_IO_gc; /* IO pin LUTn-IN1 input source */
    CCL.LUT1CTRLC = CCL_INSEL2_IO_gc;   /* IO pin LUTn-IN2 input source */
	
//Configure Truth Tables
    CCL.TRUTH0 = 0x40; /* Truth 0: 64 */
    CCL.TRUTH1 = 0x20; /* Truth 1: 32 */
	
//Enable LUT0 output on IO pin
    CCL.LUT0CTRLA = CCL_OUTEN_bm;     /* Output Enable: enabled */

//Enable LUTs
    CCL.LUT0CTRLA |= CCL_ENABLE_bm;    /* LUT Enable: enabled */
    CCL.LUT1CTRLA = CCL_ENABLE_bm;    /* LUT Enable: enabled */
	
//Enable CCL module
    CCL.CTRLA = CCL_ENABLE_bm;         /* Enable: enabled */
}

int main(void)
{
    PORT_init();
    CCL_init();
    while (1) 
    {
        ;		
    }
}

SR Latch Code Example

#include <avr/io.h>

void PORT_init (void);
void CCL_init(void);

/**
 * \brief Initialize ports
 */
void PORT_init (void)
{

    PORTA.DIR &= ~PIN1_bm;          //PA1 - LUT0 IN[1]
    PORTC.DIR &= ~PIN1_bm;          //PC1 - LUT1 IN[1]
	
    PORTA.DIR |= PIN3_bm;	        //PA3 - LUT0 output

}

/**
 * \brief Initialize CCL peripheral
 */
void CCL_init(void)
{

//configure inputs for used LUTs
    CCL.LUT0CTRLB = CCL_INSEL0_MASK_gc	/* LUTn-IN0 input masked */
                    | CCL_INSEL1_IO_gc; /* IO pin LUTn-IN1 input source */
    CCL.LUT0CTRLC = CCL_INSEL2_MASK_gc; /* LUTn-IN2 input masked */

    CCL.LUT1CTRLB = CCL_INSEL0_MASK_gc	/* LUTn-IN0 input masked */
                    | CCL_INSEL1_IO_gc; /* IO pin LUTn-IN1 input source */
    CCL.LUT1CTRLC = CCL_INSEL2_MASK_gc; /* LUTn-IN2 input masked */

//Configure Truth Tables
    CCL.TRUTH0 = 0x01; /* Truth 0: 1 */
    CCL.TRUTH1 = 0x01; /* Truth 1: 1 */

// Configure filter
    CCL.LUT0CTRLA = CCL_FILTSEL_FILTER_gc;      /* Enable filter*/
    CCL.LUT1CTRLA = CCL_FILTSEL_FILTER_gc;      /* Enable filter*/

//Enable sequential logic for LUT0 and LUT1
    CCL.SEQCTRL0 = CCL_SEQSEL0_RS_gc;
		
//Enable LUT0 output on IO pin
    CCL.LUT0CTRLA |= CCL_OUTEN_bm;     /* Output Enable: enabled */
	
//Enable LUTs
    CCL.LUT0CTRLA |= CCL_ENABLE_bm;    /* LUT Enable: enabled */
    CCL.LUT1CTRLA |= CCL_ENABLE_bm;    /* LUT Enable: enabled */
	
//Enable CCL module
    CCL.CTRLA = CCL_ENABLE_bm;         /* Enable: enabled */
}


int main(void)
{
    PORT_init();
    CCL_init();
    /* Replace with your application code */
    while (1) 
    {
        ;		
    }
}