Clock Failure Detection and Switching Mechanism is a new feature introduced in ATmega328PB. This digital logic detects the failure of the Low power crystal oscillator, Full swing crystal oscillator, and external clocks. If a failure is detected, this logic will automatically switch the clock to 1MHz internal RC system clock.
The Clock Failure Detection mechanism for the device is enabled by an active high fuse. When the CFD fuse is enabled, 128kHz oscillator will be enabled and the CFD circuit works using that clock.
CFD will be automatically disabled when the chip enters power save/down sleep mode. It will be enabled by itself when the chip returns to active mode. CFD will be enabled only when the system frequency is greater than 256kHz.