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Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security

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14 DMA Controller (XDMAC)
14.6 Linked List Descriptor Operation

Introduction
Features
Reference Document
1 Configuration Summary
2 Block Diagram
3 Signal Description
4 Microchip Recommended Power Management Solutions
5 Safety and Security Features
6 Event System
7 Package and Pinout
8 System Interconnect and Security (SIS)
9 Cortex-A7 Processor (Arm)
10 External Interrupt Controller (EIC)
11 Debug and Test
12 NIC-400 Global Programmer’s View (NICGPV)
13 Bus Matrix (MATRIX)
14 DMA Controller (XDMAC)
15 MEMORIES
16 Static Memory Controller (SMC)
17 Universal DDR Memory Controller (UDDRC)
18 DDR/LPDDR Physical Interface (DDR3PHY)
19 Boot Strategies
20 SYSTEM CONTROLLER SUBSYSTEM
21 System Controller Write Protection (SYSCWP)
22 General Purpose Backup Registers (GPBR)
23 Dual Watchdog Timer (DWDT)
24 Reset Controller (RSTC)
25 Real-Time Timer (RTT)
26 Real-Time Clock (RTC)
27 Shutdown Controller (SHDWC)
28 64-bit Periodic Interval Timer (PIT64B)
29 Chip Identifier (CHIPID)
30 OTP Memory Controller (OTPC)
31 Special Function Registers (SFR)
32 Special Function Registers Backup (SFRBU)
33 Slow Clock Controller (SCKC)
34 Clock Generator
35 Power Management Controller (PMC)
36 Parallel Input/Output Controller (PIO)
37 ANALOG SUBSYSTEM
38 Analog-to-Digital Converter (ADC) Controller
39 Analog Comparator Controller (ACC)
40 IMAGE SUBSYSTEM
41 Camera Serial Interface (CSI)
42 CSI-2 Demultiplexer Controller (CSI2DC)
43 Image Sensor Controller (ISC)
44 AUDIO SUBSYSTEM
45 Inter-IC Sound Multi-Channel Controller (I2SMCC)
46 Synchronous Serial Controller (SSC)
47 Sony/Philips Digital Interface Receiver (SPDIFRX)
48 Sony/Philips Digital Interface Transmitter (SPDIFTX)
49 Pulse Density Microphone Controller (PDMC)
50 Asynchronous Sample Rate Converter (ASRC)
51 CRYPTOGRAPHY SUBSYSTEM
52 TrustZone Advanced Encryption Standard Bridge (TZAESB)
53 TrustZone AES Bridge Address Space Controller (TZAESBASC)
54 Advanced Encryption Standard (AES)
55 Secure Hash Algorithm (SHA)
56 Triple Data Encryption Standard (TDES)
57 Random Number Generator (TRNG)
58 Integrity Check Monitor (ICM)
59 Classical Public Key Cryptography Controller (CPKCC)
60 Security Module (SECUMOD)
61 CONNECTIVITY SUBSYSTEM
62 Gigabit Ethernet MAC (GMAC)
63 Flexible Serial Communication Controller (FLEXCOM)
64 Quad Serial Peripheral Interface (QSPI)
65 Secure Digital MultiMedia Card Controller (SDMMC)
66 Controller Area Network (MCAN)
67 Timer Counter (TC)
68 Pulse Width Modulation Controller (PWM)
69 USB SUBSYSTEM
70 USB Type-C™ Port Controller (TCPC)
71 USB 2.0 PHY
72 USB Device High Speed Port (UDPHS)
73 USB Host High Speed Port (UHPHS)
74 Electrical Characteristics
75 Mechanical Characteristics
76 Marking
77 Ordering Information
78 Glossary
79 Revision History
Microchip Information

14.6 Linked List Descriptor Operation

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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