14.4 DMA Controller Peripheral Connections

DMA hardware requests are the same for XDMAC0 and XDMAC1. XDMAC2 is memory-to-memory dedicated, there is no hardware interface.

Table 14-1. DMA Channels Definitions (XDMAC0 and XDMAC1)
Instance Name Channel Transmit/Receive DMA Channel Hardware Interface Number Comments
ADC Receive 0
AES Transmit 1
AES Receive 2
FLEXCOM0 Receive 5
FLEXCOM0 Transmit 6
FLEXCOM1 Receive 7
FLEXCOM1 Transmit 8
FLEXCOM2 Receive 9
FLEXCOM2 Transmit 10
FLEXCOM3 Receive 11
FLEXCOM3 Transmit 12
FLEXCOM4 Receive 13
FLEXCOM4 Transmit 14
FLEXCOM5 Receive 15
FLEXCOM5 Transmit 16
FLEXCOM6 Receive 17
FLEXCOM6 Transmit 18
FLEXCOM7 Receive 19
FLEXCOM7 Transmit 20
FLEXCOM8 Receive 21
FLEXCOM8 Transmit 22
FLEXCOM9 Receive 23
FLEXCOM9 Transmit 24
FLEXCOM10 Receive 25
FLEXCOM10 Transmit 26
FLEXCOM11 Receive 27
FLEXCOM11 Transmit 28
I2SMCC0 Receive 33
I2SMCC0 Transmit 34
I2SMCC1 Receive 35
I2SMCC1 Transmit 36
PDMC0 Receive 37
PDMC1 Receive 38
PWM Transmit 39
QSPI0 Receive 40
QSPI0 Transmit 41
QSPI1 Receive 42
QSPI1 Transmit 43
SSC0 Receive 44
SSC0 Transmit 45
SSC1 Receive 46
SSC1 Transmit 47
SHA Transmit 48
SPDIFRX Receive 49
SPDIFTX Transmit 50
TC0 Receive 51
TC1 Receive 52
TDES Receive 53
TDES Transmit 54
ASRC R0 55
ASRC T0 56
ASRC R1 57
ASRC T1 58
ASRC R2 59
ASRC T2 60
ASRC R3 61
ASRC T3 62
TC0_CHANNEL1 CPA 63
TC1_CHANNEL1 CPA 64
TC0_CHANNEL1 CPB 65
TC1_CHANNEL1 CPB 66
TC0_CHANNEL1 CPC 67
TC1_CHANNEL1 CPC 68
TC0_CHANNEL1 ETRG 69
TC1_CHANNEL1 ETRG 70
Reserved 71-126 Do not use
Reserved 127 Memory-to-memory transfer