18.4 Register Summary

Note:

For reserved register addresses or reserved register bits, writes have no effect and reads return 0. Unless specified otherwise, control register bits are assumed active-high.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00 ... 0x03	Reserved
0x04	DDR3PHY_PIR	31:24	INITBYP	ZCALBYP	LOCKBYP	CLRSR
		23:16						CTLDINIT	DLLBYP	ICPC
		15:8								RVTRN
		7:0	QSTRN	DRAMINIT	DRAMRST	ITMSRST	ZCAL	DLLLOCK	DLLSRST	INIT
0x08	DDR3PHY_PGCR	31:24	LBMODE	LBGDQS	LBDQSS					PDDISDX
		23:16	ZCKSEL[1:0]					RANKEN
		15:8	IOLB	CKINV	CKDV[1:0]				CKEN
		7:0				DFTLMT[1:0]		DFTCMP	DQSCFG	ITMDMD
0x0C	DDR3PHY_PGSR	31:24
		23:16
		15:8							RVEIRR	RVERR
		7:0	DFTERR	DTIERR	DTERR	DTDONE	DIDONE	ZCDONE	DLDONE	IDONE
0x10	DDR3PHY_DLLGCR	31:24
		23:16	BPS200
		15:8
		7:0
0x14	DDR3PHY_ACDLLCR	31:24	DLLDIS	DLLSRST
		23:16						ATESTEN
		15:8					MFWDLY[2:0]			MFBDLY[2]
		7:0	MFBDLY[1:0]
0x18	DDR3PHY_PTR0	31:24
		23:16			TITMSRST[3:0]				TDLLLOCK[11:10]
		15:8	TDLLLOCK[9:2]
		7:0	TDLLLOCK[1:0]		TDLLSRST[5:0]
0x1C	DDR3PHY_PTR1	31:24						TDINIT1[7:5]
		23:16	TDINIT1[4:0]					TDINIT0[18:16]
		15:8	TDINIT0[15:8]
		7:0	TDINIT0[7:0]
0x20	DDR3PHY_PTR2	31:24						TDINIT3[9:7]
		23:16	TDINIT3[6:0]							TDINIT2[16]
		15:8	TDINIT2[15:8]
		7:0	TDINIT2[7:0]
0x24	DDR3PHY_ACIOCR	31:24			RSTIOM	RSTPDR	RSTPDD	RSTODT
		23:16		RANKPDR				CSPDD
		15:8		RANKODT			CKPDR			CKPDD
		7:0			CKODT	ACPDR	ACPDD	ACODT	ACOE	ACIOM
0x28	DDR3PHY_DXCCR	31:24
		23:16								AWDT
		15:8	RVSEL	DQSNRST			DQSNRES[3:0]
		7:0	DQSRES[3:0]				DXPDR	DXPDD	DXIOM	DXODT
0x2C	DDR3PHY_DSGCR	31:24	CKEOE	RSTOE	ODTOE	CKOE			NL2OE	NL2PD
		23:16				ODTPDD				CKEPDD
		15:8				FXDLAT	NOBUB	DQSGE[2:0]
		7:0	DQSGX[2:0]			LPDLLPD	LPIOPD	ZUEN	BDISEN	PUREN
0x30	DDR3PHY_DCR	31:24				DDR2T
		23:16
		15:8							DDRTYPE[1:0]
		7:0	MPRDQ	PDQ[2:0]			DDR8BNK	DDRMD[2:0]
0x34	DDR3PHY_DTPR0	31:24	TCCD	TRC[5:0]						TRRD[3]
		23:16	TRRD[2:0]			TRAS[4:0]
		15:8	TRCD[3:0]				TRP[3:0]
		7:0	TWTR[2:0]			TRTP[2:0]			TMRD[1:0]
0x38	DDR3PHY_DTPR1	31:24			TDQSCKmax[2:0]			TDQSCKmin[2:0]
		23:16	TRFC[7:0]
		15:8					TRTODT	TMOD[1:0]		TFAW[5]
		7:0	TFAW[4:0]					TRTW	TAOND/ TAOFD[1:0]
0x3C	DDR3PHY_DTPR2	31:24				TDLLK[9:5]
		23:16	TDLLK[4:0]					TCKE[3:1]
		15:8	TCKE[0]	TXP[4:0]					TXS[9:8]
		7:0	TXS[7:0]
0x40	DDR3PHY_MR0_DDR3	31:24
		23:16
		15:8				PD	WR[2:0]			DR
		7:0	TM	CL3	CL2	CL1	BT	CL0	BL[1:0]
0x40	DDR3PHY_MR0_DDR2	31:24
		23:16
		15:8				PD	WR[2:0]			DR
		7:0	TM	CL[2:0]			BT	BL[2:0]
0x44	DDR3PHY_MR1_DDR3	31:24
		23:16
		15:8				QOFF	TDQS		RTT2
		7:0	LEVEL	RTT1	DIC1	AL[1:0]		RTT0	DIC0	DE
0x44	DDR3PHY_MR1_DDR2	31:24
		23:16
		15:8				QOFF	RDQS	DQS	OCD[2:1]
		7:0	OCD[0]	RTT1	AL[2:0]			RTT0	DIC	DE
0x44	DDR3PHY_MR1_LPDDR2	31:24
		23:16
		15:8
		7:0	nWR[2:0]			WC	BT	BL[2:0]
0x44	DDR3PHY_MR1_LPDDR3	31:24
		23:16
		15:8
		7:0	nWR[2:0]					BL[2:0]
0x48	DDR3PHY_MR2_DDR3	31:24
		23:16
		15:8	RSVD[4:0]					RTTWR[1:0]
		7:0	SRT	ASR	CWL[2:0]			PASR[2:0]
0x48	DDR3PHY_MR2_DDR2	31:24
		23:16
		15:8	RSVD[4:0]
		7:0	SRF				DCC	PASR[2:0]
0x48	DDR3PHY_MR2_LPDDR2	31:24
		23:16
		15:8
		7:0	RSVD[3:0]				RL/WL[3:0]
0x48	DDR3PHY_MR2_LPDDR3	31:24
		23:16
		15:8
		7:0	RSVD[3:0]				RL/WL[3:0]
0x4C	DDR3PHY_MR3_DDR3	31:24
		23:16
		15:8	RSVD[12:5]
		7:0	RSVD[4:0]					MPR	MPRLOC[1:0]
0x4C	DDR3PHY_MR3_EMR3_DDR2	31:24
		23:16
		15:8	RSVD[15:8]
		7:0	RSVD[7:0]
0x4C	DDR3PHY_MR3_LPDDR2	31:24
		23:16
		15:8
		7:0	RSVD[3:0]				DS[3:0]
0x4C	DDR3PHY_MR3_LPDDR3	31:24
		23:16
		15:8
		7:0	RSVD[3:0]				PDCTL[1:0]		DQODT[1:0]
0x50	DDR3PHY_ODTCR	31:24
		23:16								WRODT0
		15:8
		7:0								RDODT0
0x54	DDR3PHY_DTAR	31:24	DTMPR	DTBANK[2:0]			DTROW[15:12]
		23:16	DTROW[11:4]
		15:8	DTROW[3:0]				DTCOL[11:8]
		7:0	DTCOL[7:0]
0x58	DDR3PHY_DTDR0	31:24	DTBYTE3[7:0]
		23:16	DTBYTE2[7:0]
		15:8	DTBYTE1[7:0]
		7:0	DTBYTE0[7:0]
0x5C	DDR3PHY_DTDR1	31:24	DTBYTE7[7:0]
		23:16	DTBYTE6[7:0]
		15:8	DTBYTE5[7:0]
		7:0	DTBYTE4[7:0]
0x60 ... 0xBF	Reserved
0xC0	DDR3PHY_DCUAR	31:24
		23:16
		15:8					ATYPE	INCA	CSEL[1:0]
		7:0	CSADDR[3:0]				CWADDR[3:0]
0xC4	DDR3PHY_DCUDR	31:24	CDATA[31:24]
		23:16	CDATA[23:16]
		15:8	CDATA[15:8]
		7:0	CDATA[7:0]
0xC8	DDR3PHY_DCURR	31:24
		23:16	XCEN	RCEN	SCOF	SONF	NFAIL[7:4]
		15:8	NFAIL[3:0]				EADDR[3:0]
		7:0	SADDR[3:0]				DINST[3:0]
0xCC	DDR3PHY_DCULR	31:24	XLEADDR[3:0]
		23:16							IDA	LINF
		15:8	LCNT[7:0]
		7:0	LEADDR[3:0]				LSADDR[3:0]
0xD0	DDR3PHY_DCUGCR	31:24
		23:16
		15:8	RCSW[15:8]
		7:0	RCSW[7:0]
0xD4	DDR3PHY_DCUTPR	31:24	TDCUT3[7:0]
		23:16	TDCUT2[7:0]
		15:8	TDCUT1[7:0]
		7:0	TDCUT0[7:0]
0xD8	DDR3PHY_DCUSR0	31:24
		23:16
		15:8
		7:0						CFULL	CFAIL	RDONE
0xDC	DDR3PHY_DCUSR1	31:24	LPCNT[7:0]
		23:16	FLCND[7:0]
		15:8	RDCNT[15:8]
		7:0	RDCNT[7:0]
0xE0 ... 0xFF	Reserved
0x0100	DDR3PHY_BISTRR	31:24							BCKSEL[2:1]
		23:16	BCKSEL[0]				BDXSEL	BDPAT[1:0]		BDMEN
		15:8	BACEN	BDXEN	BSONF	NFAIL[7:3]
		7:0	NFAIL[2:0]			BINF	BMODE	BINST[2:0]
0x0104	DDR3PHY_BISTMSKR0	31:24				ODTMSK				CSMSK
		23:16				CKEMSK	WEMSK	BAMSK[2:0]
		15:8	AMSK[15:8]
		7:0	AMSK[7:0]
0x0108	DDR3PHY_BISTMSKR1	31:24
		23:16					CASMSK	RASMSK	DMMSK[1:0]
		15:8
		7:0							DQMSK[1:0]
0x010C	DDR3PHY_BISTWCR	31:24
		23:16
		15:8	BWCNT[15:8]
		7:0	BWCNT[7:0]
0x0110	DDR3PHY_BISTLSR	31:24	SEED[31:24]
		23:16	SEED[23:16]
		15:8	SEED[15:8]
		7:0	SEED[7:0]
0x0114	DDR3PHY_BISTAR0	31:24		BBANK[2:0]			BROW[15:12]
		23:16	BROW[11:4]
		15:8	BROW[3:0]				BCOL[11:8]
		7:0	BCOL[7:0]
0x0118	DDR3PHY_BISTAR1	31:24
		23:16
		15:8	BAINC[11:4]
		7:0	BAINC[3:0]				BMRANK[1:0]		BRANK[1:0]
0x011C	DDR3PHY_BISTAR2	31:24		BMBANK[2:0]			BMROW[15:12]
		23:16	BMROW[11:4]
		15:8	BMROW[3:0]				BMCOL[11:8]
		7:0	BMCOL[7:0]
0x0120	DDR3PHY_BISTUDPR	31:24	BUDP1[15:8]
		23:16	BUDP1[7:0]
		15:8	BUDP0[15:8]
		7:0	BUDP0[7:0]
0x0124	DDR3PHY_BISTGSR	31:24	CASBER[1:0]		RASBER[1:0]		DMBER[3:0]
		23:16
		15:8
		7:0						BDXERR	BACERR	BDONE
0x0128	DDR3PHY_BISTWER	31:24	DXWER[15:8]
		23:16	DXWER[7:0]
		15:8	ACWER[15:8]
		7:0	ACWER[7:0]
0x012C	DDR3PHY_BISTBER0	31:24	ABER[31:24]
		23:16	ABER[23:16]
		15:8	ABER[15:8]
		7:0	ABER[7:0]
0x0130	DDR3PHY_BISTBER1	31:24							ODTBER[1:0]
		23:16							CSBER[1:0]
		15:8							CKEBER[1:0]
		7:0	WEBER[1:0]		BABER[5:0]
0x0134	DDR3PHY_BISTBER2	31:24	DQBER[31:24]
		23:16	DQBER[23:16]
		15:8	DQBER[15:8]
		7:0	DQBER[7:0]
0x0138	DDR3PHY_BISTWCSR	31:24	DXWCNT[15:8]
		23:16	DXWCNT[7:0]
		15:8	ACWCNT[15:8]
		7:0	ACWCNT[7:0]
0x013C	DDR3PHY_BISTFWR0	31:24				ODTWEBS				CSWEBS
		23:16				CKEWEBS	WEWEBS	BAWEBS[2:0]
		15:8	AWEBS[15:8]
		7:0	AWEBS[7:0]
0x0140	DDR3PHY_BISTFWR1	31:24
		23:16					CASWEBS	RASWEBS	DMWEBS[1:0]
		15:8	DQWEBS[15:8]
		7:0	DQWEBS[7:0]
0x0144 ... 0x017F	Reserved
0x0180	DDR3PHY_ZQ0CR0	31:24	ZQPD	ZCAL	ZCALBYP	ZDEN	ZDATA[27:24]
		23:16	ZDATA[23:16]
		15:8	ZDATA[15:8]
		7:0	ZDATA[7:0]
0x0184	DDR3PHY_ZQ0CR1	31:24
		23:16
		15:8
		7:0	ZPROG[7:0]
0x0188	DDR3PHY_ZQ0SR0	31:24	ZDONE	ZERR			ZCTRL[27:24]
		23:16	ZCTRL[23:16]
		15:8	ZCTRL[15:8]
		7:0	ZCTRL[7:0]
0x018C	DDR3PHY_ZQ0SR1	31:24
		23:16
		15:8
		7:0	OPU[1:0]		OPD[1:0]		ZPU[1:0]		ZPD[1:0]
0x0190 ... 0x01BF	Reserved
0x01C0	DDR3PHY_DX0GCR	31:24
		23:16								R0RVSL[2]
		15:8	R0RVSL[1:0]		RTTOAL	RTTOH[1:0]		DQRTT	DQSRTT	DSEN[1]
		7:0	DSEN[0]	DQSRPD	DXPDR	DXPDD	DXIOM	DQODT	DQSODT	DXEN
0x01C4	DDR3PHY_DX0GSR0	31:24
		23:16
		15:8	DTPASS[2:0]							DTIERR
		7:0				DTERR				DTDONE
0x01C8	DDR3PHY_DX0GSR1	31:24
		23:16			RVPASS[1:0]					RVIERR
		15:8				RVERR
		7:0			DQSDFT[1:0]					DFTERR
0x01CC	DDR3PHY_DX0DLLCR	31:24	DLLDIS	DLLSRST
		23:16					SDLBMODE	ATESTEN	SDPHASE[3:2]
		15:8	SDPHASE[1:0]		SSTART[1:0]		MFWDLY[2:0]			MFBDLY[2]
		7:0	MFBDLY[1:0]		SFWDLY[2:0]			SFBDLY[2:0]
0x01D0	DDR3PHY_DX0DQTR	31:24
		23:16
		15:8
		7:0	DQDLY1[3:0]				DQDLY0[3:0]
0x01D4	DDR3PHY_DX0DQSTR	31:24			DMDLY[3:0]				DQSNDLY[2:1]
		23:16	DQSNDLY[0]	DQSDLY[2:0]
		15:8			R0DGPS[1:0]
		7:0						R0DGSL[2:0]
0x01D8 ... 0x01FF	Reserved
0x0200	DDR3PHY_DX1GCR	31:24
		23:16								R0RVSL[2]
		15:8	R0RVSL[1:0]		RTTOAL	RTTOH[1:0]		DQRTT	DQSRTT	DSEN[1]
		7:0	DSEN[0]	DQSRPD	DXPDR	DXPDD	DXIOM	DQODT	DQSODT	DXEN
0x0204	DDR3PHY_DX1GSR0	31:24
		23:16
		15:8	DTPASS[2:0]							DTIERR
		7:0				DTERR				DTDONE
0x0208	DDR3PHY_DX1GSR1	31:24
		23:16			RVPASS[1:0]					RVIERR
		15:8				RVERR
		7:0			DQSDFT[1:0]					DFTERR
0x020C	DDR3PHY_DX1DLLCR	31:24	DLLDIS	DLLSRST
		23:16					SDLBMODE	ATESTEN	SDPHASE[3:2]
		15:8	SDPHASE[1:0]		SSTART[1:0]		MFWDLY[2:0]			MFBDLY[2]
		7:0	MFBDLY[1:0]		SFWDLY[2:0]			SFBDLY[2:0]
0x0210	DDR3PHY_DX1DQTR	31:24
		23:16
		15:8
		7:0	DQDLY1[3:0]				DQDLY0[3:0]
0x0214	DDR3PHY_DX1DQSTR	31:24			DMDLY[3:0]				DQSNDLY[2:1]
		23:16	DQSNDLY[0]	DQSDLY[2:0]
		15:8			R0DGPS[1:0]
		7:0						R0DGSL[2:0]