18.4.6 DDR3PHY PHY Timing Register 0


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
			TITMSRST[3:0]				TDLLLOCK[11:10]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			1	0	0	0	1	0


Bit	15	14	13	12	11	10	9	8
	TDLLLOCK[9:2]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	0	1	0	1	1	1	1


Bit	7	6	5	4	3	2	1	0
	TDLLLOCK[1:0]		TDLLSRST[5:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	0	0	1	1	0	1	1

Bits 21:18 – TITMSRST[3:0] ITM Soft Reset Time

Number of configuration clock (PLLDDR/4) cycles during which the ITM soft reset pin must remain asserted when the soft reset is applied to the ITMs. This must correspond to a value that is equal to or more than 8 PLLDDR clock cycles.

Bits 17:6 – TDLLLOCK[11:0] DLL Lock Time

Number of configuration clock (PLLDDR/4) cycles for the DLL to stabilize and lock, i.e. number of clock cycles from when the DLL reset pin is de-asserted to when the DLL has locked and is ready for use. Default value corresponds to 5.12 µs at 533 MHz.

Bits 5:0 – TDLLSRST[5:0] DLL Soft Reset Time

Number of configuration clock (PLLDDR/4) cycles during which the DLL soft reset pin must remain asserted when the soft reset is triggered in DDR3PHY_PIR. This must correspond to a value that is equal to or more than 50 ns or 8 controller clock cycles, whichever is bigger. Default value corresponds to 50 ns at 533 MHz.

Name:	DDR3PHY_PTR0
Offset:	0x18
Reset:	0x0022AF9B
Property:	Read/Write