70.7.9 TCPC Power Status Mask Register
The following configuration values are valid for all listed bit names of this register:
0: Interrupt masked.
1: Interrupt unmasked.
| Name: | TCPC_PSM |
| Offset: | 0x14 |
| Reset: | 0xFF |
| Property: | Read/Write |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| INIT | SRCVBUS | VBUSDETE | VBUS | SNKVBUS | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 1 | 1 | 1 | 1 |