38.6 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	ADC_CR	31:24
		23:16
		15:8
		7:0				CMPRST	SWFIFO		START	SWRST
0x04	ADC_MR	31:24	USEQ	ALWAYS1	TRANSFER[1:0]		TRACKTIM[3:0]
		23:16	ANACH				STARTUP[3:0]
		15:8	PRESCAL[7:0]
		7:0		FWUP	SLEEP		TRGSEL[2:0]
0x08	ADC_SEQR1	31:24	USCH8[3:0]				USCH7[3:0]
		23:16	USCH6[3:0]				USCH5[3:0]
		15:8	USCH4[3:0]				USCH3[3:0]
		7:0	USCH2[3:0]				USCH1[3:0]
0x0C	ADC_SEQR2	31:24	USCH16[3:0]				USCH15[3:0]
		23:16	USCH14[3:0]				USCH13[3:0]
		15:8	USCH12[3:0]				USCH11[3:0]
		7:0	USCH10[3:0]				USCH9[3:0]
0x10	ADC_CHER	31:24	CH31	CH30
		23:16
		15:8	CH15	CH14	CH13	CH12	CH11	CH10	CH9	CH8
		7:0	CH7	CH6	CH5	CH4	CH3	CH2	CH1	CH0
0x14	ADC_CHDR	31:24	CH31	CH30
		23:16
		15:8	CH15	CH14	CH13	CH12	CH11	CH10	CH9	CH8
		7:0	CH7	CH6	CH5	CH4	CH3	CH2	CH1	CH0
0x18	ADC_CHSR	31:24	CH31	CH30
		23:16
		15:8	CH15	CH14	CH13	CH12	CH11	CH10	CH9	CH8
		7:0	CH7	CH6	CH5	CH4	CH3	CH2	CH1	CH0
0x1C ... 0x1F	Reserved
0x20	ADC_LCDR	31:24				CHNBOSR[4:0]
		23:16
		15:8	LDATA[15:8]
		7:0	LDATA[7:0]
0x20	ADC_LCDR (NO_OSR)	31:24
		23:16
		15:8	NO_OSR_CHNBOSR[3:0]				NO_OSR_LDATA[11:8]
		7:0	NO_OSR_LDATA[7:0]
0x24	ADC_IER	31:24						COMPE	GOVRE	DRDY
		23:16					TEMPCHG	EOS
		15:8
		7:0			RXOVR	RXUDR	RXCHUNK	RXFULL	RXEMPTY	RXRDY
0x28	ADC_IDR	31:24						COMPE	GOVRE	DRDY
		23:16					TEMPCHG	EOS
		15:8
		7:0			RXOVR	RXUDR	RXCHUNK	RXFULL	RXEMPTY	RXRDY
0x2C	ADC_IMR	31:24						COMPE	GOVRE	DRDY
		23:16					TEMPCHG	EOS
		15:8
		7:0			RXOVR	RXUDR	RXCHUNK	RXFULL	RXEMPTY	RXRDY
0x30	ADC_ISR	31:24						COMPE	GOVRE	DRDY
		23:16					TEMPCHG	EOS
		15:8
		7:0			RXOVR	RXUDR	RXCHUNK	RXFULL	RXEMPTY	RXRDY
0x34	ADC_EOC_IER	31:24	EOC31	EOC30
		23:16
		15:8	EOC15	EOC14	EOC13	EOC12	EOC11	EOC10	EOC9	EOC8
		7:0	EOC7	EOC6	EOC5	EOC4	EOC3	EOC2	EOC1	EOC0
0x38	ADC_EOC_IDR	31:24	EOC31	EOC30
		23:16
		15:8	EOC15	EOC14	EOC13	EOC12	EOC11	EOC10	EOC9	EOC8
		7:0	EOC7	EOC6	EOC5	EOC4	EOC3	EOC2	EOC1	EOC0
0x3C	ADC_EOC_IMR	31:24	EOC31	EOC30
		23:16
		15:8	EOC15	EOC14	EOC13	EOC12	EOC11	EOC10	EOC9	EOC8
		7:0	EOC7	EOC6	EOC5	EOC4	EOC3	EOC2	EOC1	EOC0
0x40	ADC_EOC_ISR	31:24	EOC31	EOC30
		23:16
		15:8	EOC15	EOC14	EOC13	EOC12	EOC11	EOC10	EOC9	EOC8
		7:0	EOC7	EOC6	EOC5	EOC4	EOC3	EOC2	EOC1	EOC0
0x44	ADC_TEMPMR	31:24
		23:16
		15:8
		7:0			TEMPCMPMOD[1:0]					TEMPON
0x48	ADC_TEMPCWR	31:24					THIGHTHRES[11:8]
		23:16	THIGHTHRES[7:0]
		15:8					TLOWTHRES[11:8]
		7:0	TLOWTHRES[7:0]
0x4C	ADC_OVER	31:24	OVRE31	OVRE30
		23:16
		15:8	OVRE15	OVRE14	OVRE13	OVRE12	OVRE11	OVRE10	OVRE9	OVRE8
		7:0	OVRE7	OVRE6	OVRE5	OVRE4	OVRE3	OVRE2	OVRE1	OVRE0
0x50	ADC_EMR	31:24		ALTCH	ADCMODE[1:0]			SIGNMODE[1:0]		TAG
		23:16	TRACKX[1:0]		ALWAYS0	ASTE		OSR[2:0]
		15:8			CMPFILTER[1:0]				CMPALL	CMPSEL[4]
		7:0	CMPSEL[3:0]					CMPTYPE	CMPMODE[1:0]
0x54	ADC_CWR	31:24	HIGHTHRES[15:8]
		23:16	HIGHTHRES[7:0]
		15:8	LOWTHRES[15:8]
		7:0	LOWTHRES[7:0]
0x58 ... 0x5B	Reserved
0x5C	ADC_CCR	31:24
		23:16
		15:8	DIFF15	DIFF14	DIFF13	DIFF12	DIFF11	DIFF10	DIFF9	DIFF8
		7:0	DIFF7	DIFF6	DIFF5	DIFF4	DIFF3	DIFF2	DIFF1	DIFF0
0x60	ADC_CDR0	31:24
		23:16
		15:8	DATA[15:8]
		7:0	DATA[7:0]
...
0xDC	ADC_CDR31	31:24
		23:16
		15:8	DATA[15:8]
		7:0	DATA[7:0]
0xE0	ADC_ACR	31:24
		23:16								SRCLCH
		15:8							IBCTL[1:0]
		7:0
0xE4	ADC_FMR	31:24
		23:16	FIFOCNT[7:0]
		15:8
		7:0	CHUNK[3:0]						ENLEVEL	ENFIFO
0xE8 ... 0xFF	Reserved
0x0100	ADC_TRGR	31:24	TRGPER[23:16]
		23:16	TRGPER[15:8]
		15:8	TRGPER[7:0]
		7:0						TRGMOD[2:0]
0x0104	ADC_COSR	31:24
		23:16
		15:8
		7:0				CSEL[4:0]
0x0108	ADC_CVR	31:24	GAINCORR[15:8]
		23:16	GAINCORR[7:0]
		15:8	OFFSETCORR[15:8]
		7:0	OFFSETCORR[7:0]
0x010C	ADC_CECR	31:24	ECORR31	ECORR30
		23:16
		15:8	ECORR15	ECORR14	ECORR13	ECORR12	ECORR11	ECORR10	ECORR9	ECORR8
		7:0	ECORR7	ECORR6	ECORR5	ECORR4	ECORR3	ECORR2	ECORR1	ECORR0
0x0110 ... 0x0117	Reserved
0x0118	ADC_WPMR	31:24	WPKEY[23:16]
		23:16	WPKEY[15:8]
		15:8	WPKEY[7:0]
		7:0						WPCREN	WPITEN	WPEN
0x011C	ADC_WPSR	31:24
		23:16	WPVSRC[15:8]
		15:8	WPVSRC[7:0]
		7:0								WPVS