9.9 Timestamp Generator

The Arm ID (GCLK29) is the source clock for the timestamp generator. It is running and is configured to use MAINCK with no divider at reset.

The Coresight 400 IP is memory-mapped into APB_DEBUG_S (0xE8800000) and the timestamp registers are at an offset of 0x43000.

To generate timestamps:
  1. Access the memory map interface of the Coresight timestamp module(1) and:
    1. Set the timestamp generator frequency value to 24 MHz by writing 24000000 to the CNTFID0 register (same as the MAINCK frequency).
    2. Enable the timestamp generator by writing 1 to the CNTCR register.
  2. Enable PPI interrupt ID29 in GIC (secure physical timer interrupt)(2).
  3. Access the generic timer coprocessor interface (CP15)(3) to:
    1. Set the counter frequency value to 24 MHz in the CNTFRQ register.
    2. Set the timer count value in the CNTP_TVAL register.
    3. Enable the Timer event by writing into the CNTP_CTL register.

When the timer expires, a PPI interrupt is generated with interrupt ID29.

Note:
  1. Refer to Arm V7A, ARCH Manual (DDI0406C), Appendix D5.2, Coresight 400 TRM (DDI0480G), Section 3.19.
  2. Refer to Cortex-A7 TRM (DDI0464F), Section 8.2.2.
  3. Refer to Arm V7A, ARCH Manual (DDI0406C), B8.2.