9.6 Media Processing Engine (MPE) with Neon Technology
The Cortex-A7 Neon Media Processing Engine (MPE) extends the Cortex-A7 functionality to provide support for the Arm v7 Advanced SIMDv2 and Vector Floating-Pointv4 (VFPv4) instruction sets. The Cortex-A7 Neon MPE supports all addressing modes and data-processing operations described in the Arm Architecture Reference Manual, Arm v7-A and Arm v7-R edition.
The Cortex-A7 Neon MPE includes the following features:
- SIMD and scalar single-precision floating-point computation
- Scalar double-precision floating-point computation
- SIMD and scalar half-precision floating-point conversion
- SIMD 8, 16, 32, and 64-bit signed and unsigned integer computation
- 8 or 16-bit polynomial computation for single-bit coefficients
- Structured data load capabilities
- Large, shared register file, addressable as:
- Thirty-two 32-bit S (single) registers
- Thirty-two 64-bit D (double) registers
- Sixteen 128-bit Q (quad) registers
Refer to the Arm Architecture Reference Manual, Arm v7-A and Arm v7-R edition for more information about the extension register set.
The operations include:
- Addition and subtraction
- Multiplication with optional accumulation
- Maximum or minimum value driven lane selection operations
- Inverse square-root approximation
- Comprehensive data-structure load instructions, including register-bank-resident table lookup
Refer to the Cortex-A7 Neon Media Processing Engine Technical Reference Manual for details of the Neon extensions.