12.5.3 Main Clock Control C
| Name: | MCLKCTRLC |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | Configuration Change Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CFDSRC[1:0] | CFDTST | CFDEN | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 3:2 – CFDSRC[1:0] Clock Failure Detection Source
This bit field controls which clock source to monitor when the Clock Failure
Detection Enable (CFDEN) bit is ‘
1’.Note: This bit field is read-only
when the CFDEN bit is ‘
1’, and both the Clock Failure
Detection (CFD) interrupt enable bit and Interrupt Type (INTTYPE) bit in the
Main Clock Interrupt Control (CLKCTRL.MCLKINTCTRL) register are
‘1’. This bit will remain read-only until a System
Reset occurs.| Value | Name | Description |
|---|---|---|
| 0x0 | CLKMAIN | Main Clock |
| 0x1 | XOSCHF | External High-Frequency Oscillator |
| 0x2 | XOSC32K | External 32.768 kHz Oscillator |
| Other | Reserved | Reserved |
Bit 1 – CFDTST Clock Failure Detection Test
This bit controls testing of the CFD functionality.
Writing a ‘0’ to this bit will clear the bit, and the ongoing
CFD test fail condition.
Writing a ‘1’ to this bit will set the bit and force a CFD fail
condition.
| Value | Description |
|---|---|
| 0 | No ongoing test of the CFD functionality |
| 1 | A CFD fail condition has been forced |
Bit 0 – CFDEN Clock Failure Detection Enable
This bit controls whether CFD is enabled or not.
Note: This bit
is read-only when this bit is ‘
1’, and both the Clock Failure
Detection (CFD) interrupt enable bit and Interrupt Type (INTTYPE) bit in the
Main Clock Interrupt Control (CLKCTRL.MCLKINTCTRL) register are
‘1’. This bit will remain read-only until a System Reset
occurs.| Value | Description |
|---|---|
| 0 | CFD is disabled |
| 1 | CFD is enabled |