25.4 Register Summary
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | CTRLA | 7:0 | CLKSEL[1:0] | CNTPRES[1:0] | SYNCPRES[1:0] | ENABLE | ||||
| 0x01 | CTRLB | 7:0 | WGMODE[1:0] | |||||||
| 0x02 | CTRLC | 7:0 | CMPDSEL | CMPCSEL | FIFTY | AUPDATE | CMPOVR | |||
| 0x03 | CTRLD | 7:0 | CMPBVAL[3:0] | CMPAVAL[3:0] | ||||||
| 0x04 | CTRLE | 7:0 | DISEOC | SCAPTUREB | SCAPTUREA | RESTART | SYNC | SYNCEOC | ||
0x05 ... 0x07 | Reserved | |||||||||
| 0x08 | EVCTRLA | 7:0 | CFG[1:0] | EDGE | ACTION | TRIGEI | ||||
| 0x09 | EVCTRLB | 7:0 | CFG[1:0] | EDGE | ACTION | TRIGEI | ||||
0x0A ... 0x0B | Reserved | |||||||||
| 0x0C | INTCTRL | 7:0 | TRIGB | TRIGA | OVF | |||||
| 0x0D | INTFLAGS | 7:0 | TRIGB | TRIGA | OVF | |||||
| 0x0E | STATUS | 7:0 | PWMACTB | PWMACTA | CMDRDY | ENRDY | ||||
0x0F | Reserved | |||||||||
| 0x10 | INPUTCTRLA | 7:0 | INPUTMODE[3:0] | |||||||
| 0x11 | INPUTCTRLB | 7:0 | INPUTMODE[3:0] | |||||||
| 0x12 | FAULTCTRL | 7:0 | CMPDEN | CMPCEN | CMPBEN | CMPAEN | CMPD | CMPC | CMPB | CMPA |
0x13 | Reserved | |||||||||
| 0x14 | DLYCTRL | 7:0 | DLYPRESC[1:0] | DLYTRIG[1:0] | DLYSEL[1:0] | |||||
| 0x15 | DLYVAL | 7:0 | DLYVAL[7:0] | |||||||
0x16 ... 0x17 | Reserved | |||||||||
| 0x18 | DITCTRL | 7:0 | DITHERSEL[1:0] | |||||||
| 0x19 | DITVAL | 7:0 | DITHER[3:0] | |||||||
0x1A ... 0x1D | Reserved | |||||||||
| 0x1E | DBGCTRL | 7:0 | FAULTDET | DBGRUN | ||||||
0x1F ... 0x21 | Reserved | |||||||||
| 0x22 | CAPTUREA | 7:0 | CAPTUREA[7:0] | |||||||
| 15:8 | CAPTUREA[11:8] | |||||||||
| 0x24 | CAPTUREB | 7:0 | CAPTUREB[7:0] | |||||||
| 15:8 | CAPTUREB[11:8] | |||||||||
0x26 ... 0x27 | Reserved | |||||||||
| 0x28 | CMPASET | 7:0 | CMPASET[7:0] | |||||||
| 15:8 | CMPASET[11:8] | |||||||||
| 0x2A | CMPACLR | 7:0 | CMPACLR[7:0] | |||||||
| 15:8 | CMPACLR[11:8] | |||||||||
| 0x2C | CMPBSET | 7:0 | CMPBSET[7:0] | |||||||
| 15:8 | CMPBSET[11:8] | |||||||||
| 0x2E | CMPBCLR | 7:0 | CMPBCLR[7:0] | |||||||
| 15:8 | CMPBCLR[11:8] | |||||||||