25.5.3 Control C
| Name: | CTRLC |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMPDSEL | CMPCSEL | FIFTY | AUPDATE | CMPOVR | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – CMPDSEL Compare D Output Select
This bit selects which waveform will be connected to output D.
| Value | Name | Description |
|---|---|---|
| 0 | PWMA | Waveform A |
| 1 | PWMB | Waveform B |
Bit 6 – CMPCSEL Compare C Output Select
This bit selects which waveform will be connected to output C.
| Value | Name | Description |
|---|---|---|
| 0 | PWMA | Waveform A |
| 1 | PWMB | Waveform B |
Bit 3 – FIFTY Fifty Percent Waveform
A write to either TCDn.CMPASET or TCDn.CMPBSET will be written to both registers
if FIFTY = ‘1’ The same is the case for TCDn.CMPACLR
and TCDn.CMPBCLR.
Bit 1 – AUPDATE Automatically Update
If this bit is written to ‘1’, synchronization at the end of the
TCD cycle is automatically requested after the Compare B Clear High
(TCDn.CMPBCLRH) register is written.
If the fifty percent waveform is enabled (FIFTY = ‘1’), writing
to either the Compare A Clear High or the Compare B Clear High
register will request a synchronization at the end of the TCD
cycle.
Bit 0 – CMPOVR Compare Output Value Override
When this bit is written to ‘1’, default values of the Waveform
Outputs A and B are overridden by the values written in the Compare x Value in
the Active state bit fields in the Control D register. See the CTRLD register
description for more details.