3 Signal Description

Table 3-1. Signal Description List
Signal Name Function Type Comments Active Level
Clocks, Oscillators and PLLs
XIN Main Oscillator Input Input – –
XOUT Main Oscillator Output Output – –
XIN32 Slow Clock Oscillator Input Input – –
XOUT32 Slow Clock Oscillator Output Output – –
AUDIOCLK Audio Clock Output – –
PCK[7:0] Programmable Clock Output Output

Reset state:

  • PIO input
  • Internal pull-up enabled
  • Schmitt trigger enabled
 –
Shutdown, Wake-up Logic
LPM Low-power Mode Output – –
SHDN Shutdown Control Output – –
WKUP[5:0] Wake-up Input Input – –
ICE and JTAG
TCK/SWCLK Test Clock/Serial Wire Clock Input – –
TDI Test Data In Input – –
TDO Test Data Out Output – –
TMS/SWDIO Test Mode Select/Serial Wire Input/Output I/O – –
JTAGSEL JTAG Selection Input – –
Reset/Test
NRST Microprocessor Reset Input – Low
TST Test Mode Select Input – –
NTRST Test Reset Signal Input – –
NRST_OUT Microprocessor Reset Output Output – Low
External Interrupt Controller - EIC
IRQ[1:0] External Interrupt Input Input – –
PIO Controller
PA[31:0] Parallel IO Controller I/O – –
PB[31:0] Parallel IO Controller I/O – –
PC[31:0] Parallel IO Controller I/O – –
PD[31:0] Parallel IO Controller I/O – –
PE[7:0] Parallel IO Controller I/O – –
External Bus Interface - EBI
D[15:0] Data Bus I/O – –
A[25:0] Address Bus Output – –
NWAIT External Wait Signal Input – Low
Static Memory Controller - SMC
NCS[3:0] Chip Select Lines Output – Low
NWR[1:0] Write Signal Output – Low
NRD Read Signal Output – Low
NWE Write Enable Output – Low
NBS[1:0] Byte Mask Signal Output – Low
NANDOE NAND Flash Output Enable Output – Low
NANDWE NAND Flash Write Enable Output – Low
DDR2/DDR3(L)/LPDDR2/LPDDR3 Controller
DDR_CLK, DDR_CLKN DDR Differential Clock Output – –
DDR_CKE DDR Clock Enable Output – High
DDR_CS DDR Controller Chip Select Output – Low
DDR_BA[2:0] Bank Select Output – Low
DDR_WE DDR Write Enable Output – Low
DDR_RAS, DDR_CAS Row and Column Signal Output – Low
DDR_A[15:0] DDR Address Bus Output – –
DDR_D[15:0] DDR Data Bus I/O – –

DDR_DQS[1:0]

DDR_DQSN[1:0]

 Differential Data Strobe I/O – –
DDR_DQM[1:0] Write Data Mask Output – –
DDR_ZQ DDR/LPDDR Calibration Input – –
DDR_VREF DDR/LPDDR Reference Input – –
DDR_RESETN DDR3 Active Low Asynchronous Reset Output – Low
DDR_ODT DDR3 On-Die Termination Output – High
Secure Data Memory Card - SDMMCx [2:0]
SDMMCx_CAL SD Card Calibration Input – Low
SDMMCx_CD SD Card/e.MMC Card Detect Input – Low
SDMMCx_CMD SD Card/e.MMC Command line I/O – –
SDMMCx_WP SD Card Connector Write Protect Signal Input – High
SDMMCx_RSTN e.MMC Reset Signal Output – Low
SDMMCx_1V8SEL SD Card Signal Voltage Selection Output – –
SDMMCx_CK SD Card/e.MMC Clock Signal Output – –
SDMMCx_DAT[3:0] SD Card I/O – –
SDMMC0_DAT[7:4] e.MMC Data Lines I/O – –
SDMMC0_DS e.MMC Data Strobe Input – –
Flexible Serial Communication Controller - FLEXCOMx [11:0]
FLEXCOMx_IO0 Transmit Data I/O – –
FLEXCOMx_IO1 Receive Data I/O – –
FLEXCOMx_IO2 Serial Clock I/O – –
FLEXCOMx_IO3 Clear To Send/
Peripheral Chip Select I/O – –
FLEXCOMx_IO4 Request To Send/
Peripheral Chip Select Output – –
FLEXCOMx_IO5 SPI Chip Select 2 Output – –
FLEXCOMx_IO6 SPI Chip Select 3 Output – –
Inter-IC Sound Multi Channel Controller - I2SMCCx [1:0]
I2SMCCx_MCK I2S Bus Clock Output – –
I2SMCCx_CK Serial Clock I/O – –
I2SMCCx_WS I2S Word Select I/O – –
I2SMCCx_DIN[3:0] Serial Data Inputs Input – –
I2SMCCx_DOUT[3:0] Serial Data Outputs Output – –
Synchronous Serial Controller - SSCx [1:0]
TDx Transmit Data Output – –
RDx Receive Data Input – –
TKx Transmit Clock I/O – –
RKx Receive Clock I/O – –
TFx Transmit Frame Sync I/O – –
RFx Receive Frame Sync I/O – –
Timer/Counter - TCx [1:0]
TCLK[5:0] TC Channel y External Clock Input Input – –
TIOA[5:0] TC Channel y I/O Line A I/O – –
TIOB[5:0] TC Channel y I/O Line B I/O – –
Quad IO SPI - QSPIx [1:0]
QSPIx_SCK QSPI Serial Clock Output – –
QSPIx_CS QSPI Chip Select Output – Low
QSPIx_IO[3:0]

QSPI I/O

QIO0 is QMOSI Host Out - Client In

QIO1 is QMISO Host In - Client Out

 I/O – –
QSPI0_IO[7:4] QSPI0 I/Os for Octal Mode I/O – –
QSPI0_SCKN Negative QSPI0 Serial Clock Output – –
QSPI0_INT QSPI Interrupt Input – Low
QSPI0_DQS QSPI0 Data Strobe Input – –
Pulse Width Modulation Controller - PWM
PWMH[3:0] Waveform Output High Output – –
PWML[3:0] Waveform Output Low Output – –
PWMFI[1:0] Fault Inputs Input – –
PWMEXTRG[1:0] External Trigger Input – –
USB High Speed Ports - A, B, C
HHSA-DP

Host Port A High Speed Data +

Device A High Speed Data +

 Analog – –
HHSA-DM

Host Port A High Speed Data -

Device A High Speed Data -

 Analog – –
HHSB-DP

Host Port B High Speed Data +

Device B High Speed Data +

 Analog – –
HHSB-DM

Host Port B High Speed Data -

Device B High Speed Data -

 Analog – –
HHSC-DP Host Port C High Speed Data + Analog – –
HHSC-DM Host Port C High Speed Data - Analog – –
HHSA-CC[2:1] Host Port A Configuration Channels 1 and 2 Analog – –
HHSA-RTUNE Host Port A Tune Analog – –
HHSB-CC[2:1] Host Port B Configuration Channels 1 and 2 Analog – –
HHSB-RTUNE Host Port B Tune Analog – –
HHSC-RTUNE Host Port C Tune Analog – –
Ethernet 10/100/1000 - GMAC0
G0_TXCK/G0_REFCK Transmit Clock or 50 MHz Reference Clock I/O – –
G0_125CK 125 MHz Clock I/O – –
G0_TXEN/G0_TXCTL Transmit Enable or Transmit Control Signal Output – –
G0_TX[3:0] Transmit Data Output – –
G0_TXER Transmit Coding Error Output – –
G0_RXCK Receive Clock Input – –
G0_RXDV/G0_CRSDV/G0_RXCTL Receive Data Valid or Carrier Sense and Data Valid or Receive Control Signal Input – –
G0_RX[3:0] Receive Data Input – –
G0_RXER Receive Error Input – –
G0_CRS Carrier Sense Input – –
G0_COL Collision Detect Input – –
G0_MDC Management Data Clock Output – –
G0_MDIO Management Data Input/Output I/O – –
G0_TSUCOMP TSU Timer Comparison Valid Output – –
Ethernet 10/100 - GMAC1
G1_TXCK/G1_REFCK Transmit Clock or 50 MHz Reference Clock I/O – –
G1_TXEN Transmit Enable Output – –
G1_TX[3:0] Transmit Data Output – –
G1_TXER Transmit Coding Error Output – –
G1_RXCK Receive Clock Input – –
G1_RXDV/G1_CRSDV Receive Data Valid or Carrier Sense and Data Valid Input – –
G1_RX[3:0] Receive Data Input – –
G1_RXER Receive Error Input – –
G1_CRS Carrier Sense Input – –
G1_COL Collision Detect Input – –
G1_MDC Management Data Clock Output – –
G1_MDIO Management Data Input/Output I/O – –
G1_TSUCOMP TSU Timer Comparison Valid Output – –
Analog-to-Digital Converter - ADC
AD[15:0] 16 Analog Inputs Analog – –
ADTRG ADC Trigger Input – –
ADVREFP ADC Reference Analog – –
Analog Comparator Controller - ACC
ACC_INP[3:0] External Positive Analog Data Inputs Input – –
ACC_INN[3:1] External Negative Analog Data Inputs Input – –
Secure Box Module - SBM
PIOBU[3:0] Tamper I/Os I/O – –
Image Sensor Controller - ISC
ISC_D[11:0] Data Input – –
ISC_HSYNC Horizontal Synchro Input – –
ISC_VSYNC Vertical Synchro Input – –
ISC_PCK Pixel clock Input – –
ISC_MCK Main clock Output – –
ISC_FIELD Field Identification Signal Input – –
Controller Area Network - CANx [5:0]
CANRXx Receive Input – –
CANTXx Transmit Output – –
Pulse Density Modulation Interface Controller - PDMCx [1:0]
PDMCx_DS[1:0] Data Input Input – –
PDMCx_CLK Clock Output Output – –
Sony Philips Digital Interface Receiver - SPDIFRX
SPDIF_RX Receive Data Input – –
Sony Philips Digital Interface Transmitter - SPDIFTX
SPDIF_TX Transmit Data Output – –
MIPI DPHY

MIPI_DP[1:0]

MIPI_DN[1:0]

 Differential Input Data Lane [1:0] Input – –
MIPI_CLKP/MIPI_CLKN Differential Input Clock Lane Input – –
MIPI_REXT Calibration Reference Resistor Input 4.02 KΩ E96 –