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Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
Introduction
Features
Reference Document
1 Configuration Summary
2 Block Diagram
3 Signal Description
4 Microchip Recommended Power Management Solutions
4.1 MCP16502 PMIC
4.2 MCP16501 PMIC
5 Safety and Security Features
5.1 Design for Safety and IEC60730 Class B Certification
5.2 Design for Security
5.3 Safety and IEC 60730 Features
5.4 Security Features
6 Event System
6.1 Real-Time Event List
6.2 Real-Time Event Mapping
7 Package and Pinout
7.1 Package
7.2 Pinout
8 System Interconnect and Security (SIS)
8.1 System Bus and Interconnect
8.2 System Interconnect Overview
8.3 Quality of Service (QoS) Overview
8.4 TrustZone Security Management
8.5 Peripheral Clocks and Security
9 Cortex-A7 Processor (Arm)
9.1 Description
9.2 Embedded Characteristics
9.3 Clocks
9.4 Power Supplies
9.5 Generic Interrupt Controller (GIC)
9.6 Media Processing Engine (MPE) with Neon Technology
9.7 Debug
9.8 Performance Monitoring Unit (PMU)
9.9 Timestamp Generator
10 External Interrupt Controller (EIC)
10.1 Description
10.2 Embedded Characteristics
10.3 Block Diagram
10.4 I/O Lines Description
10.5 Product Dependencies
10.6 Functional Description
10.7 Register Summary
11 Debug and Test
11.1 Description
11.2 Embedded Characteristics
11.3 Block Diagram
11.4 Pin Description
11.5 Functional Description
12 NIC-400 Global Programmer’s View (NICGPV)
12.1 Description
12.2 Register Summary
13 Bus Matrix (MATRIX)
13.1 Description
13.2 Embedded Characteristics
13.3 Memory Mapping
13.4 Special Bus Granting Techniques
13.5 No Default Host
13.6 Last Access Host
13.7 Fixed Default Host
13.8 Arbitration
13.9 Register Write Protection
13.10 TrustZone Extension
13.11 Register Summary
14 DMA Controller (XDMAC)
14.1 Description
14.2 Embedded Characteristics
14.3 Block Diagram
14.4 DMA Controller Peripheral Connections
14.5 Functional Description
14.6 Linked List Descriptor Operation
14.7 XDMAC Maintenance Software Operations
14.8 XDMAC Software Requirements
14.9 Register Summary
15 MEMORIES
15.1 Embedded Memories
15.2 External Memories
15.3 Product Dependencies
15.4 Special Functions in SFR/SFRBU
16 Static Memory Controller (SMC)
16.1 Description
16.2 Embedded Characteristics
16.3 Block Diagram
16.4 I/O Lines Description
16.5 Multiplexed Signals
16.6 Application Example
16.7 Product Dependencies
16.8 External Memory Mapping
16.9 Connection to External Devices
16.10 Standard Read and Write Protocols
16.11 Scrambling/Unscrambling Function
16.12 Automatic Wait States
16.13 Data Float Wait States
16.14 External Wait
16.15 Slow Clock Mode
16.16 Register Write Protection
16.17 NFC Operations
16.18 PMECC Controller Functional Description
16.19 Software Implementation
16.20 Register Summary
17 Universal DDR Memory Controller (UDDRC)
17.1 Description
17.2 Embedded Characteristics
17.3 Block Diagram
17.4 I/O Lines Description
17.5 Functional Description
17 Register Summary
18 DDR/LPDDR Physical Interface (DDR3PHY)
18.1 Description
18.2 Embedded Characteristics
18.3 Functional Description
18.4 Register Summary
19 Boot Strategies
19.1 Standard Boot Strategy
19.2 Secure Boot Strategy
19.3 Key Provisioning and Bootstrap Programming
20 SYSTEM CONTROLLER SUBSYSTEM
20.1 Block Diagram
20.2 Components
20.3 Product Dependencies
20.4 Special Functions in SFR/SFRBU
21 System Controller Write Protection (SYSCWP)
21.1 Functional Description
21.2 Register Summary
22 General Purpose Backup Registers (GPBR)
22.1 Description
22.2 Embedded Characteristics
22.3 Register Summary
23 Dual Watchdog Timer (DWDT)
23.1 Description
23.2 Embedded Characteristics
23.3 Block Diagram
23.4 Functional Description
23.5 Register Summary
24 Reset Controller (RSTC)
24.1 Description
24.2 Embedded Characteristics
24.3 Block Diagram
24.4 Functional Description
24.5 Register Summary
25 Real-Time Timer (RTT)
25.1 Description
25.2 Embedded Characteristics
25.3 Block Diagram
25.4 Functional Description
25.5 Register Summary
26 Real-Time Clock (RTC)
26.1 Description
26.2 Embedded Characteristics
26.3 Block Diagram
26.4 Product Dependencies
26.5 Functional Description
26.6 Register Summary
27 Shutdown Controller (SHDWC)
27.1 Description
27.2 Embedded Characteristics
27.3 Block Diagram
27.4 I/O Lines Description
27.5 Product Dependencies
27.6 Functional Description
27.7 Register Summary
28 64-bit Periodic Interval Timer (PIT64B)
28.1 Description
28.2 Embedded Characteristics
28.3 Block Diagram
28.4 Product Dependencies
28.5 Functional Description
28.6 Register Summary
29 Chip Identifier (CHIPID)
29.1 Description
29.2 Embedded Characteristics
29.3 Register Summary
30 OTP Memory Controller (OTPC)
30.1 Description
30.2 Embedded Characteristics
30.3 Block Diagram
30.4 Product Dependencies
30.5 Functional Description
30.6 Register Summary
31 Special Function Registers (SFR)
31.1 Description
31.2 Embedded Characteristics
31.3 Functional Description
31 Register Summary
32 Special Function Registers Backup (SFRBU)
32.1 Description
32.2 Embedded Characteristics
32.3 Register Summary
33 Slow Clock Controller (SCKC)
33.1 Description
33.2 Embedded Characteristics
33.3 Block Diagram
33.4 Functional Description
33.5 Register Summary
34 Clock Generator
34.1 Description
34.2 Embedded Characteristics
34.3 Block Diagram
34.4 Slow Clock
34.5 Main Clock
34.6 PLL Controls
35 Power Management Controller (PMC)
35.1 Description
35.2 Embedded Characteristics
35.3 Block Diagram
35.4 Processor Clock Controller
35.5 Free-Running Processor Clock
35.6 Main System Bus Clock Controller
35.7 Peripheral and Generic Clock Controller
35.8 Programmable Clock Output Controller
35.9 Ultra-Low Power Mode and Fast Start-Up
35.10 Asynchronous Partial Wake-Up
35.11 Main Crystal Oscillator Failure Detection
35.12 32.768 kHz Crystal Oscillator Frequency Monitor
35.13 MCK0 Frequency Monitor
35.14 Recommended Programming Sequence
35.15 Clock Switching Details
35.16 Register Write Protection
35.17 Register Summary
36 Parallel Input/Output Controller (PIO)
36.1 Description
36.2 Embedded Characteristics
36.3 Block Diagram
36.4 Product Dependencies
36.5 Functional Description
36.6 I/O Lines Programming Example
36.7 Register Summary
37 ANALOG SUBSYSTEM
37.1 Block Diagram
37.2 Components
37.3 Product Dependencies
37.4 Special Functions in SFR/SFRBU
38 Analog-to-Digital Converter (ADC) Controller
38.1 Description
38.2 Embedded Characteristics
38.3 Block Diagram
38.4 Product Dependencies
38.5 Functional Description
38.6 Register Summary
39 Analog Comparator Controller (ACC)
39.1 Description
39.2 Embedded Characteristics
39.3 Block Diagram
39.4 Signal Description
39.5 Product Dependencies
39.6 Functional Description
39.7 Register Summary
40 IMAGE SUBSYSTEM
40.1 Block Diagram
40.2 Components
40.3 Product Dependencies
40.4 Special Functions in SFR/SFRBU
41 Camera Serial Interface (CSI)
41.1 Description
41.2 Embedded Characteristics
41.3 I/O Lines Description
41.4 Block Diagram
41.5 Product Dependencies
41.6 Functional Description
41.7 Register Summary
42 CSI-2 Demultiplexer Controller (CSI2DC)
42.1 Description
42.2 Embedded Characteristics
42.3 Block Diagram
42.4 I/O Lines Description
42.5 Functional Description
42.6 Register Summary
43 Image Sensor Controller (ISC)
43.1 Description
43.2 Embedded Characteristics
43.3 ISC Block Diagram and Use Cases
43.4 I/O Lines Description
43.5 Product Dependencies
43.6 Functional Description
43.7 Register Summary
44 AUDIO SUBSYSTEM
44.1 Block Diagram
44.2 Components
44.3 Product Dependencies
44.4 Special Functions in SFR/SFRBU
45 Inter-IC Sound Multi-Channel Controller (I2SMCC)
45.1 Description
45.2 Embedded Characteristics
45.3 Block Diagram
45.4 I/O Lines Description
45.5 Product Dependencies
45.6 Functional Description
45.7 Register Summary
46 Synchronous Serial Controller (SSC)
46.1 Description
46.2 Embedded Characteristics
46.3 Block Diagram
46.4 Application Block Diagram
46.5 SSC Application Examples
46.6 Pin Name List
46.7 Product Dependencies
46.8 Functional Description
46.9 Register Summary
47 Sony/Philips Digital Interface Receiver (SPDIFRX)
47.1 Description
47.2 Embedded Characteristics
47.3 Block Diagram
47.4 Signal Description
47.5 Product Dependencies
47.6 Functional Description
47.7 Register Summary
48 Sony/Philips Digital Interface Transmitter (SPDIFTX)
48.1 Description
48.2 Embedded Characteristics
48.3 Block Diagram
48.4 Signal Description
48.5 Product Dependencies
48.6 Functional Description
48.7 Register Summary
49 Pulse Density Microphone Controller (PDMC)
49.1 Description
49.2 Embedded Characteristics
49.3 PDMC Block Diagram
49.4 Signal Description
49.5 Product Dependencies
49.6 Functional Description
49.7 Register Summary
50 Asynchronous Sample Rate Converter (ASRC)
50.1 Embedded Characteristics
50.2 Description
50.3 Block Diagram
50.4 Product Dependencies
50.5 Functional Description
50.6 Register Summary
51 CRYPTOGRAPHY SUBSYSTEM
51.1 Block Diagram
51.2 Components
51.3 Product Dependencies
51.4 Special Functions in SFR/SFRBU
52 TrustZone Advanced Encryption Standard Bridge (TZAESB)
52.1 Description
52.2 Embedded Characteristics
52.3 Block Diagram
52.4 Product Dependencies
52.5 Functional Description
52.6 Register Summary
53 TrustZone AES Bridge Address Space Controller (TZAESBASC)
53.1 Description
53.2 Embedded Characteristics
53.3 Block Diagram
53.4 Functional Description
53.5 Register Summary
54 Advanced Encryption Standard (AES)
54.1 Description
54.2 Embedded Characteristics
54.3 Product Dependencies
54.4 Functional Description
54.5 Register Summary
55 Secure Hash Algorithm (SHA)
55.1 Description
55.2 Embedded Characteristics
55.3 Product Dependencies
55.4 Functional Description
55.5 Register Summary
56 Triple Data Encryption Standard (TDES)
56.1 Description
56.2 Embedded Characteristics
56.3 Product Dependencies
56.4 Functional Description
56.5 Register Summary
57 Random Number Generator (TRNG)
57.1 Description
57.2 Embedded Characteristics
57.3 Block Diagram
57.4 Product Dependencies
57.5 Functional Description
57.6 Register Summary
58 Integrity Check Monitor (ICM)
58.1 Description
58.2 Embedded Characteristics
58.3 Block Diagram
58.4 Product Dependencies
58.5 Functional Description
58.6 Register Summary
59 Classical Public Key Cryptography Controller (CPKCC)
59.1 Description
59.2 Product Dependencies
59.3 Functional Description
60 Security Module (SECUMOD)
60.1 Description
60.2 Embedded Characteristics
60.3 Block Diagram
60.4 I/O Lines Description
60.5 Product Dependencies
60.6 Functional Description
60.7 Register Summary
61 CONNECTIVITY SUBSYSTEM
61.1 Block Diagram
61.2 Components
61.3 FLEXCOM Features
61.4 Product Dependencies
61.5 Special Functions in SFR/SFRBU
62 Gigabit Ethernet MAC (GMAC)
62.1 Description
62.2 Embedded Characteristics
62.3 Block Diagram
62.4 Signal Interfaces
62.5 Product Dependencies
62.6 Functional Description
62.7 Programming Interface
62 Register Summary
63 Flexible Serial Communication Controller (FLEXCOM)
63.1 Description
63.2 Embedded Characteristics
63.3 Block Diagram
63.4 I/O Lines Description
63.5 Product Dependencies
63.6 Register Accesses
63.7 USART Functional Description
63.8 SPI Functional Description
63.9 TWI Functional Description
63.10 Register Summary
64 Quad Serial Peripheral Interface (QSPI)
64.1 Description
64.2 Embedded Characteristics
64.3 Block Diagram
64.4 Signal Description
64.5 Product Dependencies
64.6 Functional Description
64.7 Register Summary
65 Secure Digital MultiMedia Card Controller (SDMMC)
65.1 Description
65.2 Embedded Characteristics
65.3 Embedded Features for SDMMC0/1/2
65.4 Reference Documents
65.5 Block Diagram
65.6 Application Block Diagram
65.7 Pin Name List
65.8 Product Dependencies
65.9 SD/SDIO Operating Mode
65.10 e.MMC Operating Mode
65.11 SDR104 / HS200 Tuning
65.12 I/O Calibration
65.13 e.MMC HS400 Timing Mode Selection
65.14 Register Summary
66 Controller Area Network (MCAN)
66.1 Description
66.2 Embedded Characteristics
66.3 Block Diagram
66.4 Product Dependencies
66.5 Functional Description
66.6 Register Summary
67 Timer Counter (TC)
67.1 Description
67.2 Embedded Characteristics
67.3 Block Diagram
67.4 Pin List
67.5 Product Dependencies
67.6 Functional Description
67.7 Register Summary
68 Pulse Width Modulation Controller (PWM)
68.1 Description
68.2 Embedded Characteristics
68.3 Block Diagram
68.4 I/O Lines Description
68.5 Product Dependencies
68.6 Functional Description
68.7 Register Summary
69 USB SUBSYSTEM
69.1 Block Diagram
69.2 Components
69.3 Product Dependencies
69.4 Special Functions in SFR/SFRBU
70 USB Type-C™ Port Controller (TCPC)
70.1 Reference Documents
70.2 Description
70.3 Embedded Characteristics
70.4 Block Diagram
70.5 Product Dependencies
70.6 Functional Description
70.7 Register Summary
71 USB 2.0 PHY
71.1 Description
71.2 Embedded Characteristics
71.3 PHY Setup Procedure
71.4 Typical Connection
71.5 Product Dependencies
72 USB Device High Speed Port (UDPHS)
72.1 Description
72.2 Embedded Characteristics
72.3 Block Diagram
72.4 Typical Connection
72.5 Product Dependencies
72.6 Functional Description
72 Register Summary
73 USB Host High Speed Port (UHPHS)
73.1 Description
73.2 Embedded Characteristics
73.3 Block Diagram
73.4 Typical Connection
73.5 Product Dependencies
73.6 Functional Description
73 Register Summary
74 Electrical Characteristics
74.1 Electrical Parameters Usage
74.2 Absolute Maximum Ratings
74.3 ESD Ratings
74.4 Recommended Operating Conditions
74.5 Recommended Power Supply Sequencing
74.6 I/O Characteristics
74.7 Embedded Analog Peripherals Characteristics
74.8 Security Module Characteristics
74.9 Power Consumption in Active Mode
74.10 Operation and Power Consumption in Low-Power Modes
75 Mechanical Characteristics
75.1 343-Ball TFBGA Mechanical Characteristics
76 Marking
77 Ordering Information
78 Glossary
79 Revision History
79.1 DS60001765B - 12/2023
79.2 DS60001765A - 03/2022
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