2.3 Memory

SRAM memories are accessed at their address in a memory space for both reads and writes at any granularity (byte, half word or word). The SRAM is 128 KB in size.

Flash memories are accessed for read at their address in memory space. Read granularity is byte, half word or word. FC erases and writes the Flash memories. The Flash memory is 1 MB in size and supports quad-word read (128-bit) and single word write (32-bit). The page size is 4 KB with 256 words per row and four rows per page.

The FC supports panel erase for the entire flash, or page erase for the unprotected pages. It supports Single Word Program (32-bit), Quad Word Program (128-bit), and row programming with a built-in DMA for reading data from the SRAM with a four- or eight-word buffer.

Additionally, there is a 32 KB Flash NVR block separate from the Main Panel block with eight pages (0 to 7) where:
  • One page is allocated to Factory Test Memory
  • One page is allocated to Cal Space (called OTP page)
  • One page is allocated to Boot/Device Configuration (BCFG)
  • Five pages are allocated to Boot Code

Each NVR page has write-protect capability.

The device memory supports a partial write feature, but using partial write-only bits that are ‘1’ can be set to ‘0’. The user can erase the entire flash memory using a dedicated FC command.