1 I2C Specification
The I2C specification was developed by Phillips Semiconductors to communicate between devices connected to a two-wire bus. Phillips recognized that there were many similarities between consumer electronics, industrial electronics, and telecommunications designs. Since the various designs often contained similar components, such as Analog-to-Digital converters (ADCs), LCDs, or EEPROMs, Phillips determined that they could simplify system design and maximize hardware efficiency by creating a communication bus that could be used to transfer data between any device connected to the bus.
This allowed designers to use devices from multiple manufacturers, or use one device in several designs. The specification also solved interfacing problems by creating a scheme that is now held as an industry standard, meaning any I2C device could communicate with any other I2C device without having to change the hardware or firmware of either device.
The I2C specification defines the bus as a two-wire, bidirectional communications scheme. One line carries the serial data (SDA), and one line carries the serial clock (SCL). Each I2C device has its unique address, either 7-bits or 10-bits in length. An I2C device can operate as either a bus master, bus slave, or both, depending on the device and application. The specification defines the data transfer rates as follows:
- Standard mode – transfer rates up to 100 Kbits/s
- Fast mode – transfer rates up to 400 Kbits/s
- Fast mode Plus – transfer rates up to 1 Mbit/s
- High-speed mode – transfer rates up to 3.4 Mbits/s
Microchip’s I2C module implements master and slave hardware that supports Standard mode, Fast mode and Fast mode Plus. Throughout this technical brief, the I2C specification will be referred to so that the reader understands both the I2C module and the I2C specification.
I2C Bus Terminology
To properly understand the language used in the specification, the following is a list of terms commonly used by the specification and found throughout this technical brief:
| Term | Description |
|---|---|
| Transmitter | The device that shifts data out onto the bus |
| Receiver | The device that shifts data in from the bus |
| Master | The device that initiates data transfer, generates the clock signal, and terminates transmission |
| Slave | The device addressed by the master |
| Multi-master | A bus with more than one device that can initiate data transfers |
| Arbitration | Procedure that ensures that only one master at a time controls the bus |
| Synchronization | Procedure to synchronize the clocks of two or more devices on the bus |
| Idle | Both the SDA and SCK lines are in a logic High state; no activity on the bus |
| Active | Any time in which one or more master devices are controlling the bus |
| Address Slave | Slave device that has received a matching address and is actively being clocked by a master |
| Matching Address | Address byte clocked into a slave that matches the value stored in one of the I2CxADR registers |
| Write Request | Master sends an address byte with the R/W bit clear; master intends to write data to the slave |
| Read Request | Master sends an address byte with the R/W bit set; master intends to receive data from a slave |
| Clock Stretching | When a device holds the clock line low to pause communications |
| Bus Collision | Condition in which the expected data on SDA is a logic high, but is sampled as a logic low |
| Bus Time-Out | Condition in which a device on the bus is holding the bus for longer than a specified period |