4 I2C Master Mode Operation

To begin any I2C communication, the master hardware checks to ensure that the bus is in an idle state, which means both the SCL and SDA lines are floating high. Master hardware monitors the Bus Free (BFRE) bit to be set, indicating the bus is idle. The master then transmits a Start condition, followed by the address of the slave it intends to communicate with. The slave address can be either 7-bit or 10-bit, depending on the application design.

In 7-bit Addressing mode, the Least Significant bit (LSb) acts as the Read/not Write (R/W) bit, while in 10-bit Addressing mode, the LSb of the address high byte is considered the R/W bit. When the R/W bit is set, the master intends to read from the slave. If the R/W bit is cleared, the master intends to write to the slave. If the addressed slave device exists on the bus, it must respond with an Acknowledge (ACK) sequence.

The master then continues to either receive data from the slave, write data to the slave, or a combination of both. Data is always transmitted Most Significant bit (MSb) first. When the master intends to halt further transmission, it transmits a Stop condition, signaling to the slave that communication is to be terminated, or a Restart condition, signaling the bus that the current master wishes to hold the bus to communicate with the same or other slaves.

Master mode is selected by configuring the MODE<2:0> bits of the I2CxCON0 register. There are four Master mode configurations:

  • I2C Master mode with 7-bit address
  • I2C Master mode with 10-bit address
  • I2C Multi-Master – Master mode with 7-bit address and Slave mode with two 7-bit addresses with masking
  • I2C Multi-Master – Master mode with 7-bit address and Slave mode with four 7-bit addresses.

The master device generates the SCL pulses, as well as the Start, Restart, and Stop conditions. Transmission always begins with a Start condition, and can end with either a Stop condition or Restart condition. When the master has completed all transactions, and is ready to release the bus, it will generate a Stop condition. If the master wishes to stop communicating with one slave, but wants to hold the bus to address another slave, it issues a Restart condition. Control of the bus can only be asserted when the Bus Free (BFRE) bit of the I2CxSTAT0 register is set.

The steps to initiate a transaction depend on the settings of the Address Buffer Disable (ABD) bit of the I2CxCON2 register.

When the ABD bit is clear (ABD = 0), the address buffer registers, I2CxADB0 and I2CxADB1, are active and used for slave address transmission. The module will automatically load the transmit shift register with an address stored in one of the address buffers. Software must set the Start (S) bit to initiate communication with the slave.

When the ABD bit is set (ABD = 1), the address buffers are inactive and ignored for transmission. In this case, user software must load the I2CxTXB with the slave address to begin communication, and any writing to the Start bit will be ignored.