8 Master Mode Reception

The following section describes the sequence of events when using the I2C in Master mode reception.

  1. Depending on the configuration of the Address Buffer Disable (ABD) bit, one of two methods is used to begin communication.

    When ABD is clear, the address buffers are enabled. In 7-bit Addressing mode, the 7-bit slave address is loaded into the I2CxADB1 register with the R/W bit clear. In 10-bit Addressing mode, the high address byte is loaded into the I2CxADB1 register with the R/W bit set, and the low address byte is loaded into the I2CxADB0 register. The number of data bytes to be transmitted in one packet is loaded into the I2CxCNT register, and the first byte of data is loaded into the I2CxTXB transmit register. After these registers are loaded, master software must set the Start bit to begin communication. Master hardware must wait for BFRE to be set before transmitting the Start condition to avoid bus collisions.

    When ABD is set, the address buffers are disabled. In this case, the number of data bytes to be transmitted in one packet must be loaded into the I2CxCNT register before loading the transmit register. In 7-bit Addressing mode, the slave address is loaded into I2CxTXB with the R/W bit set. Writing to the I2CxTXB register will automatically issue a Start condition via module hardware once the BFRE is set. In 10-bit Addressing mode, the slave’s high address byte with the R/W bit clear is loaded into the I2CxTXB register. Once the BFRE bit is set, module hardware shifts out the high address byte. In both 7-bit and 10-bit Addressing modes, when ABD is set, writes to the Start bit are ignored.

  2. Master hardware waits for the BFRE bit to be set, then shifts out the Start condition. Module hardware sets the Master Mode Active (MMA) and Start Condition Interrupt Flag (SCIF) bits.
  3. Master transmits either the 7-bit slave address with R/W set or the 10-bit high address byte with R/W set.

    In 10-bit mode, module hardware waits for the ACK/NACK from the slave. If a NACK is received, module hardware immediately issues a Stop condition. If an ACK is received, module hardware shifts out the 10-bit address low byte.

  4. Master hardware monitors the SDA line to determine if a slave is stretching the clock, and waits until the SDA line is sampled high.
  5. Master hardware transmits the 9th clock pulse, clocking in the slave’s ACK/NACK response.
  6. If the master receives an ACK, hardware clocks the data byte from the slave into the shift register.

    If the master receives a NACK, and the ABD bit is clear, master hardware generates a Stop condition, or sets the MDR bit if RSEN is also set and waits for software to set the Start bit to generate a Restart condition.

    If the master receives a NACK and the ABD bit is set, master hardware generates a Stop condition, or sets the MDR bit if RSEN is also set and waits for software to load new address data into I2CxTXB. Software writes to the Start bit are ignored.

  7. If the previous data is still in the I2CxRXB register (RXBF = 1) when the first 7 bits of the new byte is received into the shift register, the MDR bit is set, and the clock is stretched after the 7th falling edge of SCL. This allows master software to read I2CxRXB, which clears the RXBF bit, and prevents a receive buffer overflow. Once the RXBF bit is clear, hardware releases SCL.
  8. Master hardware clocks in the 8th bit of the new data byte into the shift register, then transfers the complete byte into I2CxRXB, sets the I2CxRXIF and the RXBF bits. I2CxCNT is decremented by one.
  9. Master hardware checks I2CxCNT for a ‘0’ value.

    If I2CxCNT is not ‘0’, hardware transmits the value of the Acknowledge Data (ACKDT) bit as the ACK value to the slave. Master hardware will then continue receive data into the shift register, repeating steps 7-9 until I2CxCNT is ‘0’. It is up to the user to configure the ACKDT bit appropriately. In most cases, the ACKDT bit would have to be clear, so that the slave receives an ACK (logic low level on SDA during the 9th SCL pulse).

    If I2CxCNT is ‘0’, hardware transmits the value of the Acknowledge End of Count (ACKCNT) bit as the ACK value to the slave. It is up to the user to properly define the ACKCNT bit. In most cases, this bit is set, indicating a NACK condition. When master hardware detects the NACK on the bus, hardware will also generate a Stop condition. If the ACKCNT bit is clear, an ACK will be issued, and hardware will not automatically generate the Stop condition.